Export 174 results:
Author Title [ Type] Year Filters: First Letter Of Last Name is B [Clear All Filters]
"UML-based specifications of an embedded system oriented to HW/SW partitioning: a case study",
Languages for system specification: Selected contributions on UML, systemC, system Verilog, mixed-signal systems, and property specification from FDL'03, Norwell, MA, USA, Kluwer Academic Publishers, pp. 71-84, 2004.
"Self-Organizing Real-Time Services in Mobile Ad Hoc Networks",
Self-Organization in Embedded Real-Time Systems: Springer New York, pp. 55-74, 2013.
"MULTICUBE: Multi-Objective Design Space Exploration of Multi-Core Architectures",
VLSI 2010 Annual Symposium, vol. 105, Netherlands, Springer, pp. 47-63, 2011.
"MULTICUBE: Multi-Objective Design Space Exploration of Multi-Core Architectures",
VLSI 2010 Annual Symposium, vol. 105, Netherlands, Springer, pp. 47-63, 2011.
"The MULTICUBE Design Flow",
Multi-objective Design Space Exploration of Multiprocessor SoC Architectures: Springer New York, pp. 3-17, 2011.
"The MULTICUBE Design Flow",
Multi-objective Design Space Exploration of Multiprocessor SoC Architectures: Springer New York, pp. 3-17, 2011.
"A Methodology for Bridging the Gap between UML and Codesign",
UML for SOC Design, Dordrecht, The Netherlands, Springer, pp. 119-146, 2005.
"Interaction between Fault Attack Countermeasures and the Resistance against Power Analysis Attacks",
Fault Analysis in Cryptography: Springer Berlin Heidelberg, pp. 257-272, 2012.
"Fault Attacks, Injection Techniques and Tools for Simulation",
Hardware Security and Trust: Design and Deployment of Integrated Circuits in a Threatened Environment, First edition; 2016: Springer, pp. 149-167, 2017.
"Design Space Exploration of Parallel Architectures",
Multi-objective design space exploration of multiprocessor SoC architectures: the MULTICUBE approach, New York, USA, Springer, 2011.
"A Design Flow and Evaluation Framework for DPA-resistant Instruction Set Extensions",
Cryptographic Hardware and Embedded Systems (CHES), vol. 5747, Lausanne, Switzerland, Springer Berlin Heidelberg, pp. 205-219, September, 2009.
"A Design Flow and Evaluation Framework for DPA-resistant Instruction Set Extensions",
Cryptographic Hardware and Embedded Systems (CHES), vol. 5747, Lausanne, Switzerland, Springer Berlin Heidelberg, pp. 205-219, September, 2009.
"AETHER: Self-Adaptive Networked Entities: Autonomous Computing Elements for Future Pervasive Applications and Technologies",
Reconfigurable Computing: From FPGAs to Hardware/Software Codesign, New York, USA, Springer, pp. 149–184, 2011.
"AETHER: Self-Adaptive Networked Entities: Autonomous Computing Elements for Future Pervasive Applications and Technologies",
Reconfigurable Computing: From FPGAs to Hardware/Software Codesign, New York, USA, Springer, pp. 149–184, 2011.