@article {18591,
	title = {Black-Hat High-Level Synthesis: Myth or Reality?},
	journal = {IEEE Transactions on Very Large Scale Integration Systems},
	year = {In Press},
	doi = {10.1109/TVLSI.2018.2884742},
	author = {Pilato, Christian and Basu, Kanad and Regazzoni, Francesco and Karri, Ramesh}
}
@article {18569,
	title = {Compact Circuits for Combined AES},
	journal = {Journal of Cryptographic Engineering},
	year = {In Press},
	author = {Banik, Subhadeep and Bogdanov, Andrey and Regazzoni, Francesco}
}
@article {18567,
	title = {Customized Instructions for Protection Against Memory Integrity Attacks},
	journal = {IEEE Embedded Systems Letters},
	year = {In Press},
	author = {Roy, Debapriya Basu and Alam, Manaar and Bhattacharya, Sarani and Govindan, Vidya and Regazzoni, Francesco and Chakraborty, Rajat Subhra and Mukhopadhyay, Debdeep}
}
@article {18568,
	title = {Towards Low Energy Stream Ciphers},
	journal = {IACR Transactions on Symmetric Cryptology},
	year = {In Press},
	author = {Banik, Subhadeep and Mikhalev, Vasily and Armknecht, Frederik and Isobe, Takanori and Meier, Willi and Bogdanov, Andrey and Watanabe, Yuhei and Regazzoni, Francesco}
}
@conference {18590,
	title = {High-Level Synthesis of Benevolent Trojans},
	booktitle = {Proceedings of the IEEE Design, Automation and Test in Europe Conference (DATE)},
	year = {2019},
	author = {Pilato, Christian and Basu, Kanad and Shayan, Mohammed and Regazzoni, Francesco and Karri, Ramesh}
}
@article {18536,
	title = {Credit Card Fraud Detection: A Realistic Modeling and a Novel Learning Strategy},
	journal = {IEEE Transactions on Neural Networks and Learning Systems},
	year = {2018},
	pages = {1-14},
	keywords = {Amplitude modulation, Area measurement, Companies, Concept drift, Credit card fraud detection, Credit cards, learning in nonstationary environments, Learning systems, Tools, Training, unbalanced classification.},
	issn = {2162-237X},
	doi = {10.1109/TNNLS.2017.2736643},
	author = {Dal Pozzolo, Andrea and Boracchi, Giacomo and Caelen, Olivier and Alippi, Cesare and Bontempi, Gianluca}
}
@article {18533,
	title = {Determination of the Edge of Criticality in Echo State Networks Through Fisher Information Maximization},
	journal = {IEEE Transactions on Neural Networks and Learning Systems},
	volume = {29},
	year = {2018},
	month = {March},
	pages = {706-717},
	keywords = {Echo state network (ESN), echo state networks, edge of criticality, ESN, Fisher information, Fisher information matrix, Fisher information maximization, Jacobian matrices, Learning systems, Neurons, nonparametric estimation, nonparametric estimator, nonparametric statistics, prediction error, Probability density function, recurrent neural nets, recurrent neural networks, Reservoirs, RNN, short-term memory capacity, Training},
	issn = {2162-237X},
	doi = {10.1109/TNNLS.2016.2644268},
	author = {Livi, Lorenzo and Bianchi, Filippo Maria and Alippi, Cesare}
}
@conference {18577,
	title = {Efficient Configurations for Block Ciphers with Unified ENC/DEC Paths},
	booktitle = {Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust (HOST) 2017},
	year = {2018},
	author = {Banik, Subhadeep and Bogdanov, Andrey and Regazzoni, Francesco}
}
@conference {18574,
	title = {Inverse Gating for Low Energy Block Ciphers},
	booktitle = {Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust (HOST)},
	year = {2018},
	author = {Banik, Subhadeep and Bogdanov, Andrey and Isobe, Takanori and Hiwatari, Harunaga and Akishita, Toru and Regazzoni, Francesco}
}
@article {18508,
	title = {Investigating echo state networks dynamics by means of recurrence analysis},
	journal = {IEEE Transactions on Neural Networks and Learning Systems},
	volume = {29},
	year = {2018},
	month = {02/2018},
	pages = { 427 - 439},
	abstract = {In this paper, we elaborate over the well-known
interpretability issue in echo state networks. The idea is to investigate
the dynamics of reservoir neurons with time-series analysis
techniques taken from research on complex systems. Notably, we
analyze time-series of neuron activations with Recurrence Plots
(RPs) and Recurrence Quantification Analysis (RQA), which
permit to visualize and characterize high-dimensional dynamical
systems. We show that this approach is useful in a number of
ways. First, the two-dimensional representation offered by RPs
provides a way for visualizing the high-dimensional dynamics of
a reservoir. Our results suggest that, if the network is stable,
reservoir and input denote similar line patterns in the respective
RPs. Conversely, the more unstable the ESN, the more the RP
of the reservoir presents instability patterns. As a second result,
we show that the Lmax measure is highly correlated with the
well-established maximal local Lyapunov exponent. This suggests
that complexity measures based on RP diagonal lines distribution
provide a valuable tool to quantify the degree of network stability.
Finally, our analysis shows that all RQA measures fluctuate on
the proximity of the so-called edge of stability, where an ESN
typically achieves maximum computational capability. We verify
that the determination of the edge of stability provided by such
RQA measures is more accurate than two well-known criteria
based on the Jacobian matrix of the reservoir. Therefore, we
claim that RPs and RQA-based analyses can be used as valuable
tools to design an effective network given a specific problem.},
	doi = {10.1109/TNNLS.2016.2630802},
	author = {Bianchi, Filippo Maria and Livi, Lorenzo and Alippi, Cesare}
}
@article {18512,
	title = {A Pdf-free Change Detection Test Based on Density Difference Estimation},
	journal = {IEEE Transactions on Neural Networks and Learning Systems},
	volume = {29},
	issue = {2},
	year = {2018},
	month = {11/2016},
	pages = { 324 - 334},
	chapter = {324},
	abstract = {The ability to detect 1 online changes in stationarity or time variance in a data stream is a hot research topic with striking implications. In this paper, we propose a novel probability density function-free change detection test, which is based on the least squares density-difference estimation method and operates online on multidimensional inputs. The test does not require any assumption about the underlying data distribution, and is able to operate immediately after having been configured by adopting a reservoir sampling mechanism. Thresholds requested to detect a change are automatically derived once a false positive rate is set by the application designer. Comprehensive experiments validate the effectiveness in detection of the proposed method both in terms of detection promptness and accuracy.},
	doi = {10.1109/TNNLS.2016.2619909},
	author = {Bo, Li and Alippi, Cesare and Zhao, Dongbin}
}
@conference {18588,
	title = {SCA-Resistance for AES: How Cheap Can We Go?},
	booktitle = {Progress in Cryptology {\textendash} AFRICACRYPT 2018},
	year = {2018},
	publisher = {Springer International Publishing},
	organization = {Springer International Publishing},
	address = {Cham},
	abstract = {This paper introduces a novel AES structure capable of improving the robustness against power analysis attacks while allowing for a very compact structure with a potentially negligible area and performance impact. The proposed design is based on a low entropy masking scheme, where half of the time the true value and half of the time the complemented value are used to mask the power consumption variation. The obtained experimental results suggest that the area overhead for the protection against power analysis is as low as 5{\%} LUT increase with a performance degradation of about 10{\%}. When compared with the state of the art supported on FPGAs, efficiency improvements above 6 times and a throughput improvement of at least two times higher are achieved.},
	isbn = {978-3-319-89339-6},
	author = {Chaves, Ricardo and Chmielewski, {\L}ukasz and Regazzoni, Francesco and Batina, Lejla},
	editor = {Joux, Antoine and Nitaj, Abderrahmane and Rachidi, Tajjeeddine}
}
@conference {18530,
	title = {Time series kernel similarities for predicting Paroxysmal Atrial Fibrillation from ECGs},
	booktitle = { IJCNN 2018 : International Joint Conference on Neural Networks},
	year = {2018},
	month = {07/2018},
	publisher = {IEEE},
	organization = {IEEE},
	address = {Rio, Brazil},
	author = {Bianchi, Filippo Maria and Livi, Lorenzo and Ferrante, Alberto and Milosevic, Jelena and Malek, Miroslaw}
}
@conference {18538,
	title = {Critical echo state network dynamics by means of Fisher information maximization},
	booktitle = {2017 International Joint Conference on Neural Networks (IJCNN)},
	year = {2017},
	month = {May},
	keywords = {Asymptotic stability, critical phase transitions, echo state network, edge of criticality, Electronic mail, ESN, Estimation, estimation theory, FIM, Fisher information matrix, Fisher information maximization, hidden neurons activations, high short term memory capacity, input signal, low prediction error, network dynamics, network theory (graphs), Neurons, optimisation, Probability density function, recurrent neural nets, Reservoirs, signal processing, statistics, Tuning, unsupervised approach, unsupervised learning},
	doi = {10.1109/IJCNN.2017.7965941},
	author = {Bianchi, Filippo Maria and Livi, Lorenzo and Jenssen, Robert and Alippi, Cesare}
}
@inbook {18571,
	title = {Fault Attacks, Injection Techniques and Tools for Simulation},
	booktitle = {Hardware Security and Trust: Design and Deployment of Integrated Circuits in a Threatened Environment},
	year = {2017},
	pages = {149-167},
	publisher = {Springer},
	organization = {Springer},
	edition = {First edition; 2016},
	author = {Piscitelli, Roberta and Bhasin, Shivam and Regazzoni, Francesco}
}
@article {18535,
	title = {An Incremental Change Detection Test Based on Density Difference Estimation},
	journal = {IEEE Transactions on Systems, Man, and Cybernetics: Systems},
	volume = {47},
	year = {2017},
	month = {Oct},
	pages = {2714-2726},
	keywords = {Big data framework, Change detection, change detection method, density difference estimation, Estimation, false positive rates, Feature extraction, Histograms, incremental change detection test, incremental computing, incremental least squares density difference change detection method (LSDD-Inc), Internet of Things, Kernel, least squares approximations, least squares density difference, linear combination, LSDD, LSDD values, nonoverlapping data windows, probability, Probability density function, probability density function (pdf)-free, probability density functions, process continuous data streams, Training},
	issn = {2168-2216},
	doi = {10.1109/TSMC.2017.2682502},
	author = {Bu, Li and Zhao, Dongbin and Alippi, Cesare}
}
@article {18561,
	title = {An Investigation of Sources of Randomness Within Discrete Gaussian Sampling},
	journal = {IACR Cryptology ePrint Archive},
	volume = {2017},
	year = {2017},
	pages = {298},
	author = {Brannigan, S{\'e}amus and Smyth, Neil and Oder, Tobias and Valencia, Felipe and O{\textquoteright}Sullivan, Elizabeth and G{\"u}neysu, Tim and Regazzoni, Francesco}
}
@article {18540,
	title = {A Kolmogorov-Smirnov Test to Detect Changes in Stationarity in Big Data},
	journal = {IFAC-PapersOnLine},
	volume = {50},
	year = {2017},
	pages = {14260 - 14265},
	abstract = {The paper proposes an effective change detection test for online monitoring data streams by inspecting the least squares density difference (LSDD) features extracted from two non-overlapped windows. The first window contains samples associated with the pre-change probability distribution function (pdf) and the second one with the post-change one (that differs from the former if a change in stationarity occurs). This method can detect changes by also controlling the false positive rate. However, since the window sizes is fixed after the test has been configured (it has to be small to reduce the execution time), the method may fail to detect changes with small magnitude which need more samples to reach the requested level of confidence. In this paper, we extend our work to the Big Data framework by applying the Kolmogorov-Smirnov test (KS test) to infer changes. Experiments show that the proposed method is effective in detecting changes.},
	keywords = {change detection test, KS test, LSDD},
	issn = {2405-8963},
	doi = {https://doi.org/10.1016/j.ifacol.2017.08.1821},
	url = {http://www.sciencedirect.com/science/article/pii/S2405896317324436},
	author = {Zhao, Dongbin and Bu, Li and Alippi, Cesare and Wei, Qinglai}
}
@article {18532,
	title = {Multiplex visibility graphs to investigate recurrent neural network dynamics},
	journal = {Nature-Scientific reports},
	volume = {7},
	year = {2017},
	month = {03/2017},
	pages = {44037-44049},
	chapter = {44037},
	doi = {doi:10.1038/srep44037},
	author = {Bianchi, Filippo Maria and Livi, Lorenzo and Alippi, Cesare and Jenssen, Robert}
}
@conference {18488,
	title = {Adaptable AES implementation with power-gating support},
	booktitle = {International Conference on Computing Frontiers CF{\textquoteright}16},
	series = {Proceedings of the ACM International Conference on Computing Frontiers},
	year = {2016},
	month = {05/2016},
	pages = {331-334},
	publisher = {ACM Ney York, NY, USA},
	organization = {ACM Ney York, NY, USA},
	address = {Como, Italy},
	abstract = {In this paper, we propose a reconfigurable design of the Advanced Encryption Standard capable of adapting at runtime to the requirements of the target application. Reconfiguration is achieved by activating only a specific subset of all the instantiated processing elements. Further, we explore the effectiveness of power gating and clock gating methodologies to minimize the energy consumption of the processing elements not involved in computation.},
	keywords = {AES implementation, power analysis attacks, power modeling},
	isbn = {978-1-4503-4128-8},
	doi = {10.1145/2903150.2903488},
	url = {http://doi.acm.org/10.1145/2903150.2903488},
	author = {Banik, Subhadeep and Bogdanov, Andrey and Fanni, Tiziana and Sau, Carlo and Raffo, Luigi and Palumbo, Francesca and Regazzoni, Francesco}
}
@conference {18578,
	title = {Atomic-AES: A Compact Implementation of the AES Encryption/Decryption Core},
	booktitle = {Proceedings of 17th International Conference on Cryptology in India (INDOCRYPT) 2016},
	year = {2016},
	author = {Banik, Subhadeep and Bogdanov, Andrey and Regazzoni, Francesco}
}
@proceedings {18514,
	title = {CCM: Controlling the Change Magnitude in High Dimensional Data},
	journal = {In Proceedings of the 2nd INNS Conference on Big Data 2016 (INNS Big Data 2016)},
	year = {2016},
	month = {10/2016},
	pages = {1-10},
	address = {Thessaloniki, Greece},
	abstract = {Change-detection algorithms are often tested on real-world datasets where changes are synthetically introduced. While this common practice allows generating multiple datasets to obtain stable performance measures, it is often quite arbitrary since the change magnitude is seldom controlled. Thus, experiments { in particular those on multivariate and high-dimensional data. We here present a rigorous framework for introducing changes having a controlled magnitude in multivariate datasets. In particular, we introduce changes by directly roto-translating the data, and we measure the change magnitude by the symmetric
Kullback-Leibler divergence between pre- ad post-change distributions. We present an iterative algorithm that identities the roto-translation parameters yielding the desired change magnitude, and we prove its convergence analytically. We also illustrate our MATLAB framework that introduces changes having a controlled magnitude in real-world datasets, which is made publicly available for download.
},
	author = {Alippi, Cesare and Boracchi, Giacomo and Carrera, Diego}
}
@conference {18447,
	title = {Change Detection in Multivariate Datastreams: Likelihood and  Detectability Loss},
	booktitle = {25th International Joint Conference on Artificial Intelligence (IJCAI-16)},
	year = {2016},
	month = {07/2016},
	address = { New York, USA},
	abstract = {We address the problem of detecting changes in multivariate datastreams, and we investigate the intrinsic difficulty that change-detection methods have to face when the data-dimension scales. In particular, we consider the general approach that detects changes by comparing the distribution of the log-likelihood of the datastream over different time windows. Despite the fact that this approach constitutes the frame for several change-detection methods, its effectiveness when the dimension of data scales has never been investigated, which is indeed the goal of our paper. We show that the magnitude of the change can be naturally measured by the symmetric Kullback-Leibler divergence between the pre- and post-change distributions, and that the detectability of a change of a given magnitude worsens when the data-dimension increases. This structural problem, which we refer to as detectability loss, is due to the linear relationship existing between the variance of the log-likelihood and the data dimension, and reveals to be harmful even at low data-dimensions (say, 10). We analytically derive the detectability loss on Gaussian-distributed datastreams, and empirically demonstrate that this problem holds also on real-world datasets.},
	author = {Alippi, Cesare and Boracchi, Giacomo and Carrera, Diego and Roveri, Manuel}
}
@conference {18449,
	title = {Ensemble LSDD-based Change Detection Tests},
	booktitle = {IEEE-INNS  International Joint Conference on Neural Networks (IJCNN16)},
	year = {2016},
	month = {07/2016},
	address = {Vancouver, Canada},
	abstract = {The least squares density difference change detection test (LSDD-CDT) has proven to be an effective method in detecting concept drift by inspecting features derived from the discrepancy between two probability density functions (pdfs). The first pdf is associated with the concept drift free case, the second to the possible post change one. Interestingly, the method permits to control the ratio of false positives. This paper introduces and investigates the performance of a family of LSDD methods constructed by exploring different ensemble options applied to the basic CDT procedure. Experiments show that most of proposed methods are characterized by improved performance in change detection once compared with the direct ensemble-free counterpart.},
	author = {Bu, Li and Alippi, Cesare and Zhao, Dongbin}
}
@conference {18485,
	title = {Evaluating the Impact of Environmental Factors on Physically Unclonable Functions},
	booktitle = {International Symposium on Field-Programmable Gate Arrays FPGA 2016},
	series = {Proceedings of the 2016 ACM/SIGDA},
	year = {2016},
	month = {02/2016},
	pages = {279},
	publisher = {ACM New York, NY, USA},
	organization = {ACM New York, NY, USA},
	address = {Monterey, CA, USA},
	abstract = {Fabrication process introduces some inherent variability to the attributes of transistors (in particular length, widths, oxide thickness). As a result, every chip is physically unique. Physical uniqueness of microelectronics components can be used for multiple security applications. Physically Unclonable Functions (PUFs) are built to extract the physical uniqueness of microelectronics components and make it usable for secure applications.

However, the microelectronics components used by PUFs designs suffer from external, environmental variations that impact the PUF behavior. Variations of temperature gradients during manufacturing can bias the PUF responses. Variations of temperature or thermal noise during PUF operation change the behavior of the circuit, and can introduce errors in PUF responses. Detailed knowledge of the behavior of PUFs operating over various environmental factors is needed to reliably extract and demonstrate uniqueness of the chips.

In this work, we present a detailed and exhaustive analysis of the behavior of two PUF designs, a ring oscillator PUF and a timing path violation PUF. We have implemented both PUFs using FPGA fabricated by Xilinx, and analyzed their behavior while varying temperature and supply voltage. Our experiments quantify the robustness of each design, demonstrate their sensitivity to temperature and show the impact which supply voltage has on the uniqueness of the analyzed PUFs.
},
	isbn = {978-1-4503-3856-1},
	doi = {10.1145/2847263.2847308},
	url = {http://doi.acm.org/10.1145/2847263.2847308},
	author = {Bellon, Sebastien and Favi, Claudio and Malek, Miroslaw and Macchetti, Marco and Regazzoni, Francesco}
}
@article {18543,
	title = {Model Complexity, Regularization, and Sparsity [Guest Editorial]},
	year = {2016},
	keywords = {Adaptation models, Computational complexity, machine learning, Sparse matrices, Special issues and sections},
	doi = {10.1109/MCI.2016.2602071},
	author = {Alippi, Cesare and Boracchi, Giacomo and Wohlberg, Brendt}
}
@conference {18484,
	title = {Round gating for low energy block ciphers},
	booktitle = {2016 IEEE International Symposium on Hardware Oriented Security and Trust, HOST},
	year = {2016},
	month = {05/2016},
	pages = {55-60},
	publisher = {IEEE Computer Society},
	organization = {IEEE Computer Society},
	address = {McLean, VA, USA},
	abstract = {Pushed by the pervasive diffusion of devices operated by battery or by the energy harvested, energy has become one of the most important parameter to be optimized for embedded systems. Particularly relevant would be to optimize the energy consumption of security primitives. In this paper we explore design techniques for implementing block ciphers in a low energy fashion. We concentrate on round based implementation and we discuss how gating, applied at round level can affect and improve the energy consumption of the most common lightweight block cipher currently used in the internet of things. Additionally, we discuss how to needed gating wave can be generated. Experimental results show that our technique is able to reduce the energy consumption in most block ciphers by over 60\% while incurring only a minimal overhead in hardware},
	keywords = {algorithm design and analysis, ciphers, clocks, computer architecture, energy consumption},
	isbn = {978-1-4673-8826-9},
	doi = {10.1109/HST.2016.7495556},
	url = {http://dx.doi.org/10.1109/HST.2016.7495556},
	author = {Banik, Subhadeep and Bogdanov, Andrey and Regazzoni, Francesco and Isobe, Takanori and Hiwatari, Harunaga and Akishita, Toru}
}
@conference {18489,
	title = {Secure architectures of future emerging cryptography},
	booktitle = {International Conference on Computing Frontiers CF{\textquoteright}16},
	series = {Proceedings of the ACM International Conference on Computing Frontiers},
	year = {2016},
	month = {05/2016},
	pages = {315-322},
	publisher = {ACM New York},
	organization = {ACM New York},
	address = {Como, italy},
	abstract = {Funded under the European Union{\textquoteright}s Horizon 2020 research and innovation programme, SAFEcrypto will provide a new generation of practical, robust and physically secure post-quantum cryptographic solutions that ensure long-term security for future ICT systems, services and applications. The project will focus on the remarkably versatile field of Lattice-based cryptography as the source of computational hardness, and will deliver optimised public key security primitives for digital signatures and authentication, as well identity based encryption (IBE) and attribute based encryption (ABE). This will involve algorithmic and design optimisations, and implementations of lattice-based cryptographic schemes addressing cost, energy consumption, performance and physical robustness. As the National Institute of Standards and Technology (NIST) prepares for the transition to a post-quantum cryptographic suite B, urging organisations that build systems and infrastructures that require long-term security to consider this transition in architectural designs; the SAFEcrypto project will provide Proof-of-concept demonstrators of schemes for three practical real-world case studies with long-term security requirements, in the application areas of satellite communications, network security and cloud. The goal is to affirm Lattice-based cryptography as an effective replacement for traditional number-theoretic public-key cryptography, by demonstrating that it can address the needs of resource-constrained embedded applications, such as mobile and battery-operated devices, and of real-time high performance applications for cloud and network management infrastructures},
	keywords = {identity based encryption, lattice-based cryptography, physical attacks, public-key cryptography},
	isbn = {978-1-4503-4128-8},
	doi = {10.1145/2903150.2907756},
	url = {http://doi.acm.org/10.1145/2903150.2907756},
	author = {O{\textquoteright}Neill, Maire and O{\textquoteright}Sullivan, Elizabeth and McWilliams, Gavin and Saarinen, Markku-Juhani and Moore, Ciara and Khalid, Ayesha and Howe, James and Del Pino, Rafael and Abdalla, Michel and Regazzoni, Francesco and Valencia, Andres Felipe and G{\"u}neysu, Tim and Oder, Tobias and Waller, Adrian and Jones, Glyn and Barnett, Anthony and Griffin, Robert and Byrne, Andrew and Ammar, Bassem and Lund, David}
}
@conference {18487,
	title = {Standard lattices in hardware},
	booktitle = {Proceedings of the 53rd Annual Design Automation Conference DAC 2016},
	series = {Proceedings of DAC },
	year = {2016},
	month = {06/2016},
	pages = {162},
	publisher = {ACM},
	organization = {ACM},
	address = {Austin, TX, USA},
	abstract = {Lattice-based cryptography has gained credence recently as a replacement for current public-key cryptosystems, due to its quantum-resilience, versatility, and relatively low key sizes. To date, encryption based on the learning with errors (LWE) problem has only been investigated from an ideal lattice standpoint, due to its computation and size efficiencies. However, a thorough investigation of standard lattices in practice has yet to be considered. Standard lattices may be preferred to ideal lattices due to their stronger security assumptions and less restrictive parameter selection process.

In this paper, an area-optimised hardware architecture of a standard lattice-based cryptographic scheme is proposed. The design is implemented on a FPGA and it is found that both encryption and decryption fit comfortably on a Spartan-6 FPGA. This is the first hardware architecture for standard lattice-based cryptography reported in the literature to date, and thus is a benchmark for future implementations. Additionally, a revised discrete Gaussian sampler is proposed which is the fastest of its type to date, and also is the first to investigate the cost savings of implementing with λ/2-bits of precision.

Performance results are promising compared to the hardware designs of the equivalent ring-LWE scheme, which in addition to providing stronger security proofs; generate 1272 encryptions per second and 4395 decryptions per second.
},
	keywords = {encryption, hardware design, lattice-based cryptography, physical attack},
	isbn = {978-1-4503-4236-0},
	doi = {10.1145/2897937.2898037},
	url = {http://doi.acm.org/10.1145/2897937.2898037},
	author = {Howe, James and Moore, Ciara and O{\textquoteright}Neill, Maire and Regazzoni, Francesco and G{\"u}neysu, Tim and Beeden, K.}
}
@conference {18490,
	title = {Topology Optimization of Wireless Localization Networks},
	booktitle = {European Wireless 2016 },
	year = {2016},
	month = {05/2016},
	address = {Oulu, Finland},
	abstract = {This paper addresses topology optimization problem for an ultra wide band (UWB) localization network, where trilateration is used to obtain the target position based on its distances from fixed and known anchors. Our goal is to minimize the number of anchors needed to localize a target, while keeping the localization uncertainty lower than a given threshold in an area of arbitrary shape with obstacles. Our propagation model accounts for the presence of line of sight (LOS) between nodes, while geometric dilution of precision (GDoP) is used to express the localization error introduced by trilateration. We propose two integer linear programming formulations to solve the problem. To handle the problems of large sizes, we use the greedy placement with pruning heuristic. We test our solutions through simulation and show that the integer linear programming is appropriate to handle reasonably sized problems, and the heuristic achieves the results, in terms of the number of anchors placed, within less
than 2\% of optimum on average.
},
	keywords = {localization network, propagation model, topology optimization, ultra wide band, wireless protocols, wireless sensor networks},
	author = {Bala{\'c}, Katarina and Akhmedov, Murodzhon and Prevostini, Mauro and Malek, Miroslaw}
}
@conference {18579,
	title = {Trojans in Early Design Steps - An Emerging Threat},
	booktitle = {TRUDEVICE Final Conference (FCTRU{\^a}16)},
	year = {2016},
	author = {Polian, Ilia and Becker, Georg and Regazzoni, Francesco}
}
@article {18482,
	title = {Automatic Application of Power Analysis Countermeasures},
	journal = {IEEE Transactions on Computers },
	volume = {64},
	issue = {2},
	year = {2015},
	month = {02/2015},
	pages = {329-341},
	type = {journal},
	chapter = {329},
	abstract = {We introduce a compiler that automatically inserts software countermeasures to protect cryptographic algorithms against power-based side-channel attacks. The compiler first estimates which instruction instances leak the most information through side-channels. This information is obtained either by dynamic analysis, evaluating an information theoretic metric over the power traces acquired during the execution of the input program, or by static analysis. As information leakage implies a loss of security, the compiler then identifies (groups of) instruction instances to protect with a software countermeasure such as random precharging or Boolean masking. As software protection incurs significant overhead in terms of cryptosystem runtime and memory usage, the compiler protects the minimum number of instruction instances to achieve a desired level of security. The compiler is evaluated on two block ciphers, AES and Clefia; our experiments demonstrate that the compiler can automatically identify and protect the most important instruction instances. To date, these software countermeasures have been inserted manually by security experts, who are not necessarily the main cryptosystem developers. Our compiler offers significant productivity gains for cryptosystem developers who wish to protect their implementations from side-channel attacks},
	keywords = {cryptographic algorithms protection, cryptography, data protection, power analysis attacks, program compilers, side-channel attacks},
	issn = {0018-9340},
	doi = {10.1109/TC.2013.219},
	url = {http://dx.doi.org/10.1109/TC.2013.219},
	author = {Bayrak, Ali Galip and Regazzoni, Francesco and Novo, David and Brisk, Philip and Standaert, Fran{\c c}ois-Xavier and Ienne, Paolo}
}
@conference {18477,
	title = {Challenges in designing trustworthy cryptographic co-processors},
	booktitle = {IEEE International Symposium on Circuits and Systems (ISCAS) 2015},
	year = {2015},
	month = {09/2015},
	pages = {2009-2012},
	publisher = {IEEE},
	organization = {IEEE},
	address = {Lisbon, Portugal},
	abstract = {Security is becoming ubiquitous in our society. However, the vulnerability of electronic devices that implement the needed cryptographic primitives has become a major issue. This paper starts by presenting a comprehensive overview of the existing attacks to cryptography implementations. Thereafter, the state-of-the-art on some of the most critical aspects of designing cryptographic co-processors are presented. This analysis starts by considering the design of asymmetrical and symmetrical cryptographic primitives, followed by the discussion on the design and online testing of True Random Number Generation. To conclude, techniques for the detection of Hardware Trojans are also discussed},
	keywords = {asymmetrical cryptographic primitives, cryptography, hardware Trojan detection techniques},
	issn = {0271-4302 },
	doi = {10.1109/ISCAS.2015.7169070},
	url = {http://dx.doi.org/10.1109/ISCAS.2015.7169070},
	author = {Regazzoni, Francesco and Graves, Ricardo and Di Natale, Giorgio and Batina, Lejla and Bhasin, Shivam and Ege, Baris and Fournaris, Apostolos P. and Mentens, Nele and Picek, Stjepan and Rozic, Vladimir and Sklavos, Nicolas and Yang, Bohan}
}
@article {18473,
	title = {Exploring Energy Efficiency of Lightweight Block Ciphers},
	journal = {(IACR) Cryptology ePrint Archive},
	volume = {2015},
	year = {2015},
	month = {09/2015},
	chapter = {847},
	abstract = {In the last few years, the field of lightweight cryptography has seen an influx in the number of block ciphers and hash functions being proposed. One of the metrics that define a good lightweight design is the energy consumed per unit operation of the algorithm. For block ciphers, this operation is the encryption of one plaintext. By studying the energy consumption model of a CMOS gate, we arrive at the conclusion that the total energy consumed during the encryption operation of an r-round unrolled architecture of any block cipher is a quadratic function in r. We then apply our model to 9 well known lightweight block ciphers, and thereby try to predict the optimal value of r at which an r-round unrolled architecture for a cipher is likely to be most energy efficient. We also try to relate our results to some physical design parameters like the signal delay across a round and algorithmic parameters like the number of rounds taken to achieve full diffusion of a difference in the plaintext/key. },
	keywords = {implementation AES, lightweight block cipher, Low Power Energy Circuits},
	url = {http://eprint.iacr.org/2015/847},
	author = {Banik, Subhadeep and Bogdanov, Andrey and Regazzoni, Francesco}
}
@conference {18474,
	title = {Exploring Energy Efficiency of Lightweight Block Ciphers},
	booktitle = {Selected Areas in Cryptography: 22nd International Conference (SAC)2015},
	series = {Lecture Notes in Computer Science},
	volume = {9566},
	year = {2015},
	month = {08/2015},
	pages = {178-194},
	publisher = {Springer},
	organization = {Springer},
	address = {Sackville, NB, Canada},
	abstract = {In the last few years, the field of lightweight cryptography has seen an influx in the number of block ciphers and hash functions being proposed. One of the metrics that define a good lightweight design is the energy consumed per unit operation of the algorithm. For block ciphers, this operation is the encryption of one plaintext. By studying the energy consumption model of a CMOS gate, we arrive at the conclusion that the energy consumed per cycle during the encryption operation of an r-round unrolled architecture of any block cipher is a quadratic function in r. We then apply our model to 9 well known lightweight block ciphers, and thereby try to predict the optimal value of r at which an r-round unrolled architecture for a cipher is likely to be most energy efficient. We also try to relate our results to some physical design parameters like the signal delay across a round and algorithmic parameters like the number of rounds taken to achieve full diffusion of a difference in the plaintext/key.},
	keywords = {AES, lightweight block cipher, Low Power Energy Circuits},
	isbn = {978-3-319-31300-9},
	issn = {0302-9743},
	doi = {10.1007/978-3-319-31301-6},
	url = {http://dx.doi.org/10.1007/978-3-319-31301-6},
	author = {Banik, Subhadeep and Bogdanov, Andrey and Regazzoni, Francesco}
}
@conference {18475,
	title = {Exploring the energy consumption of lightweight blockciphers in FPGA},
	booktitle = {International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015},
	year = {2015},
	month = {02/2016},
	pages = {1-6},
	publisher = {IEEE},
	organization = {IEEE},
	edition = {2015},
	address = {Rivera Maya, Mexico City},
	abstract = {Internet of things and cyber-physical systems requiring security functionality has pushed for the design of a number of block ciphers and hash functions specifically developed for being implemented in resource constrained devices. Initially the optimization was mainly on area and power consumption, but, nowadays the attention is more on the energy consumption. In this paper, for the first time, we look at energy consumption of lightweight block ciphers implemented in reconfigurable devices, and we analyze the effects that round unrolling might have on the energy consumed during the encryption. Concentrating on applications that require a number of parallel encryptions, we instantiate several designs on the target FPGA and we analyze how the energy consumption varies in each algorithm when changing the amount of unrolled rounds. Our results, obtained on the Xc6slx45t device of the Spartan6 family, demonstrate that Present is the most energy efficient algorithm and that the relation between the energy consumption and the number of unrolled rounds measured on FPGA is similar to the one measured on dedicated hardware.},
	keywords = {cryptography, cyber-physical systems, encryption, lightweight block cipher},
	isbn = {978-1-4673-9406-2},
	doi = {10.1109/ReConFig.2015.7393308},
	url = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=7390332},
	author = {Banik, Subhadeep and Bogdanov, Andrey and Regazzoni, Francesco}
}
@conference {18480,
	title = {Fault attacks, injection techniques and tools for simulation},
	booktitle = {10th International Conference on Design Technology of Integrated Systems in Nanoscale Era DTIS 2015},
	year = {2015},
	month = {04/2015},
	pages = {1-6},
	publisher = {IEEE},
	organization = {IEEE},
	address = {Naples, Italy},
	abstract = {Faults attacks are a serious threat to secure devices, because they are powerful and they can be performed with extremely cheap equipment. Resistance against fault attacks is often evaluated directly on the manufactured devices, as commercial tools supporting fault evaluation do not usually provide the level of details needed to assert the security of a device. Early identification of weak points would instead be very useful as it would allow to immediately apply the appropriate countermeasures directly at design time. Moving towards this goal, in this work, we survey existing fault attacks and techniques for injecting faults, and we analyze the suitability of existing electronic design automaton commodities for estimating resistance against fault attacks. Our exploration, which includes the type of attacks that can be simulated and the limitations of each considered simulation approach, is an initial step towards the development of a complete framework for asserting fault attack robustness},
	keywords = {fault attacks robustness, fault resilience, injection techniques, secure devices, security, security of data},
	isbn = {978-1-4799-1999-4},
	doi = {10.1109/DTIS.2015.7127352},
	url = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=7118811},
	author = {Piscitelli, Roberta and Bhasin, Shivam and Regazzoni, Francesco}
}
@conference {18483,
	title = {Midori: A Block Cipher for Low Energy},
	booktitle = {21st International Conference on the Theory and Application of Cryptology and Information Security ASIACRYPT 2015},
	series = {Lecture Notes in Computer Science},
	volume = {9453},
	year = {2015},
	month = {11/2015},
	pages = {411-436},
	publisher = {Springer Berlin Heidelberg},
	organization = {Springer Berlin Heidelberg},
	address = {Auckland, New Zealand},
	abstract = {In the past few years, lightweight cryptography has become a popular research discipline with a number of ciphers and hash functions proposed. The designers{\textquoteright} focus has been predominantly to minimize the hardware area, while other goals such as low latency have been addressed rather recently only. However, the optimization goal of low energy for block cipher design has not been explicitly addressed so far. At the same time, it is a crucial measure of goodness for an algorithm. Indeed, a cipher optimized with respect to energy has wide applications, especially in constrained environments running on a tight power/energy budget such as medical implants.

This paper presents the block cipher Midori (The name of the cipher is the Japanese translation for the word Green.) that is optimized with respect to the energy consumed by the circuit per bt in encryption or decryption operation. We deliberate on the design choices that lead to low energy consumption in an electrical circuit, and try to optimize each component of the circuit as well as its entire architecture for energy. An added motivation is to make both encryption and decryption functionalities available by small tweak in the circuit that would not incur significant area or energy overheads. We propose two energy-efficient block ciphers Midori128 and Midori64 with block sizes equal to 128 and 64 bits respectively. These ciphers have the added property that a circuit that provides both the functionalities of encryption and decryption can be designed with very little overhead in terms of area and energy. We compare our results with other ciphers with similar characteristics: it was found that the energy consumptions of Midori64  and Midori128  are by far better when compared ciphers like PRINCE and NOEKEON.
},
	keywords = {lightweight block cipher, low energy circuits},
	isbn = {978-3-662-48799-0},
	issn = {0302-9743},
	doi = {10.1007/978-3-662-48800-3_17},
	url = {http://dx.doi.org/10.1007/978-3-662-48800-3_17},
	author = {Banik, Subhadeep and Bogdanov, Andrey and Isobe, Takanori and Shibutani, Kyoji and Hiwatari, Harunaga and Akishita, Toru and Regazzoni, Francesco}
}
@article {18472,
	title = {Midori: (A) Block Cipher for Low Energy (Extended Version)},
	journal = {(IACR) Cryptology ePrint Archive},
	volume = {2015},
	year = {2015},
	month = {12/2015},
	chapter = {1142},
	abstract = {In the past few years, lightweight cryptography has become a popular research discipline with a number of ciphers and hash functions proposed. The designers{\textquoteright} focus has been predominantly to minimize the hardware area, while other goals such as low latency have been addressed rather recently only. However, the optimization goal of low energy for block cipher design has not been explicitly addressed so far. At the same time, it is a crucial measure of goodness for an algorithm. Indeed, a cipher optimized with respect to energy has wide applications, especially in constrained environments running on a tight power/energy budget such as medical implants. 

This paper presents the block cipher Midori that is optimized with respect to the energy consumed by the circuit per bit in encryption or decryption operation. We deliberate on the design choices that lead to low energy consumption in an electrical circuit, and try to optimize each component of the circuit as well as its entire architecture for energy. An added motivation is to make both encryption and decryption functionalities available by small tweak in the circuit that would not incur significant area or energy overheads. 

We propose two energy-efficient block ciphers Midori128 and Midori64 with block sizes equal to 128 and 64 bits respectively. These ciphers have the added property that a circuit that provides both the functionalities of encryption and decryption can be designed with very little overhead in terms of area and energy. We compare our results with other ciphers with similar characteristics: it was found that the energy consumptions of Midori64 and Midori128 are by far better when compared ciphers like PRINCE and NOEKEON. 
},
	keywords = {AES, lightweight block cipher, low energy circuits, secret-key cryptography},
	url = {http://eprint.iacr.org/2015/1142},
	author = {Regazzoni, Francesco and Banik, Subhadeep and Bogdanov, Andrey and Isobe, Takanori and Shibutani, Kyoji and Hiwatari, Harunaga and Akishita, Toru}
}
@conference {18380,
	title = {Optimizing Sensor Nodes Placement for Fault-tolerant Trilateration-based Localization},
	booktitle = {IEEE Pacific Rim International Symposium on Dependable Computing (PRDC)},
	year = {2015},
	month = {11/2015},
	address = {Zhangjiajie, China},
	author = {Bala{\'c}, Katarina and Prevostini, Mauro and Malek, Miroslaw}
}
@conference {18392,
	title = {SCV2: A model-based validation and verification approach to system-of-systems engineering},
	booktitle = {System of Systems Engineering Conference (SoSE), 2015 10th},
	year = {2015},
	month = {05/2015},
	publisher = {IEEE},
	organization = {IEEE},
	abstract = {Model-Based Systems Engineering provides an effective methodology for designing complex systems and System-of-Systems. More importantly, such an approach opens the possibility to automatically generate executable simulators from system modules using model-to-code transformations, in order to verify the system model{\textquoteright}s completeness and validate design requirements. However, the user may still need to write code segments to describe the detailed functionality of system components. In this paper, we present the SCV2 tool, which allows the simulation of big size heterogeneous/multiple-class systems and system-of-systems, imposes code-model consistency and aided statechart design through reverse code-to-model transformations, and provides query-based requirement validation and functionality verification through an intuitive user interface. Finally, we present a use-case showing the utilization of the tool in the WiBRATE FP7 project for early-stage validation of system requirements.},
	keywords = {Automated Code Generation, Model-based System Engineering, SoSE, StateCharts, SysML, System-of-Systems, Validation and Verification},
	doi = {10.1109/SYSOSE.2015.7151960},
	url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7151960},
	author = {Baddour, Rami and Paspaliaris, Alkiviadis and Herrera, Daniel Solis}
}
@conference {18476,
	title = {A survey on hardware trojan detection techniques},
	booktitle = {IEEE International Symposium on Circuits and Systems (ISCAS) 2015},
	year = {2015},
	month = {08/2015},
	pages = {2021-2024},
	publisher = {IEEE},
	organization = {IEEE},
	edition = {2015},
	address = {Lisbon, Portugal},
	abstract = {Hardware Trojans recently emerged as a serious issue for computer systems, especially for those used in critical applications such as medical or military. Trojan proposed so far can affect the reliability of a device in various ways. Proposed effects range from the leakage of secret information to the complete malfunctioning of the device. A crucial point for securing the overall operation of a device is to guarantee the absence of hardware Trojans. In this paper, we survey several techniques for detecting malicious modification of circuit introduced at different phases of the design flow. We also highlight their capabilities limitations in thwarting hardware Trojans.},
	keywords = {hardware Trojan detection techniques, integrated circuit reliability},
	isbn = {978-1-4799-8391-9},
	issn = {0271-4302},
	doi = {10.1109/ISCAS.2015.7169073},
	url = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=7152138},
	author = {Bhasin, Shivam and Regazzoni, Francesco}
}
@article {18058,
	title = {A Combined Design-Time/Test-Time Study of the Vulnerability of Sub-Threshold Devices to Low Voltage Fault Attacks},
	journal = {IEEE Transactions on Emerging Topics in Computing},
	volume = {PP},
	issue = {99},
	year = {2014},
	month = {04/2014},
	abstract = {The continuous scaling of VLSI technology and the possibility to run circuits in subthreshold voltage range make it possible to implement standard cryptographic primitives within the very limited circuit and power budget of RFID devices. However, such cryptographic implementations raise concerns regarding their vulnerability to both active and passive side-channel attacks. In particular, when focusing on RFID targeted designs, it is important to evaluate their resistance against low cost physical attacks. A low cost fault injection attack can be mounted, for example, by lowering the supply voltage of the chip with the goal of causing setup time violations. In this paper, we provide an in-depth characterization of a chip implementation of the AES cipher. The chip has been designed using a 65nm low power standard cell library and operates in a subthreshold voltage range. We first show that it is possible to inject faults (through lowering the supply voltage) compliant with the fault models required to perform attacks against the AES cipher. We then investigate the possibility of predicting, at design time, which parts of the chip are more likely to be sensitive to such fault injection attacks and produce the desirable (from the point of view of the attacker) faulty behavior. Identifying such sensitive logic signals allows us to suggest to the designer a tailored countermeasure strategy for thwarting these attacks, with a minimal impact on the circuit{\textquoteright}s performance.},
	issn = {2168-6750},
	doi = {10.1109/TETC.2014.2316509},
	author = {Barenghi, Alessandro and Hocquet, C{\'e}dric and Bol, David and Standaert, Fran{\c c}ois-Xavier and Regazzoni, Francesco and Koren, Israel}
}
@conference {18091,
	title = {DRuiD: Designing Reconfigurable Architectures with Decision-making Support},
	booktitle = {19th Asia and South Pacific Design Automation Conference (ASP-DAC)},
	year = {2014},
	month = {01/2014},
	address = {Singapore},
	url = {http://home.deib.polimi.it/gpalermo/papers/ASPDAC14DRUID.pdf},
	author = {Mariani, Giovanni and Meeuws, Roel and Palermo, Gianluca and Sima, Vlad-Mihai and Silvano, Cristina and Bertels, Koen}
}
@conference {18464,
	title = {Embedded Systems Education: Job Market Expectations},
	booktitle = {Workshop on Embedded and Cyber-Physical Systems Education (WESE) },
	year = {2014},
	month = {10/2014},
	publisher = {ACM},
	organization = {ACM},
	address = {New Delhi, India},
	abstract = {In the fifteen years since the first Embedded Systems Design Master studies were proposed the embedded systems world has radically changed. The spectrum of application areas has increased beyond any expectation, and the increasing presence of embedded systems in the physical world has led to "cyber-physical systems." Devices tend to become a commodity in many cases, while sensors and IPs acquire a larger share of the market. The whole industrial ecosystem is changing as well, with "application" companies becoming increasingly present and SMEs emerging as major players. It becomes mandatory to reconsider the competences and capacities that should be provided in a Master of Science course oriented to Embedded Systems Design, so as to meet new and diverse requests that come from job market and prospective employers. Within the frame of the Nano-Tera Swiss Federal program (www.nano-tera.ch), the educational project Future Embedded Systems Education (FESTE) aimed at identifying requests coming from the job market, so as to outline the renewed professional profile for young Embedded Systems Designers. The results indicate that programming, networking, real time and system architecture know-how combined with soft skills such as teamwork and communication are in demand and frequently come under disguised names such as automation or control engineering.},
	keywords = {Cyber-Physical Systems Education, embedded systems, Nano Tera program},
	isbn = {978-1-4503-3090-9},
	url = {http://doi.acm.org/10.1145/2829957.2829961},
	author = {Sami, Mariagiovanna and Malek, Miroslaw and Bondi, Umberto and Regazzoni, Francesco}
}
@conference {18088,
	title = {Malicious Wave: a Survey on Actively Tampering Using Electromagnetic Glitch},
	booktitle = {International Symposium on Electromagnetic Compatibility 2014},
	year = {2014},
	month = {08/2014},
	author = {Bhasin, Shivam and Maistri, Paolo and Regazzoni, Francesco}
}
@conference {18227,
	title = {Risk Assessment of Atrial Fibrillation: a Failure Prediction Approach},
	booktitle = {41st Computing in Cardiology Conference (CinC)},
	year = {2014},
	month = {09/2014},
	publisher = {IEEE Computer Society},
	organization = {IEEE Computer Society},
	address = {Cambridge, MA, USA},
	abstract = {We present a methodology for identifying patients who have experienced Paroxysmal Atrial Fibrillation (PAF) among a given subjects population. Our work is intended as an initial step towards the design of an unobtrusive system for concurrent detection and monitoring of chronic cardiac conditions.

Our methodology comprises two stages: off-line training and on-line analysis. During training the most significant features are selected using machine-learning methods, without relying on a manual selection based on previous knowledge. Analysis is based on two phases: feature extraction and detection of PAF patients. Light-weight algorithms are employed in the feature extraction phase, allowing the on-line implementation of this step on wearable and resource-constrained sensor nodes. The detection phase employs techniques borrowed from the field of failure prediction. While these algorithms have found extensive applications in diverse scenarios, their application to automated cardiac analysis has not been sufficiently investigated.

Obtained results, in terms of performance, are comparable to similar efforts in the field. Nonetheless, the proposed method employs computationally simpler and more efficient algorithms, which are compatible with the computational constraints of state-of-the-art body sensor nodes.},
	url = {http://andreas-dittrich.eu/2014/06/risk-assessment-of-atrial-fibrillation-a-failure-prediction-approach},
	author = {Milosevic, Jelena and Dittrich, Andreas and Ferrante, Alberto and Malek, Miroslaw and Rojas Quiros, Camilo and Braojos, Rub{\'e}n and Ansaloni, Giovanni and Atienza, David}
}
@article {18467,
	title = {Simulation-Time Security Margin Assessment against Power-Based Side Channel Attacks},
	journal = {(IACR) Cryptology ePrint Archive},
	volume = {2014},
	year = {2014},
	month = {05/2014},
	chapter = {307},
	abstract = {A sound design time evaluation of the security of a digital device is a goal which has attracted a great amount of research effort lately. Common security metrics for the attack consider either the theoretical leakage of the device, or assume as a security metric the number of measurements needed in order to be able to always recover the secret key. In this work we provide a combined security metric taking into account the computational effort needed to lead the attack, in combination with the quantity of measurements to be performed, and provide a practical lower bound for the security margin which can be employed by a secure hardware designer. This paper represents a first exploration of a design-time security metric incorporating the computational effort required to lead a power- based side channel attack in the security level assessment of the device. We take into account in our metric the possible presence of masking and hiding schemes, and we assume the best measurement conditions for the attacker, thus leading to a conservative estimate of the security of the device. We provide a practical validation of our security metric through an analysis of transistor-level accurate power simulations of a 128-bit AES core implemented on a 65 nm library.},
	keywords = {AES, implementation, Side-channel analysis},
	author = {Barenghi, Alessandro and Pelosi, Gerardo and Regazzoni, Francesco}
}
@conference {18470,
	title = {Single-Photon Avalanche Diodes (SPADs) for quantum random number generators and beyond},
	booktitle = {19th Asia and South Pacific Design Automation Conference (ASP-DAC) 2014},
	year = {2014},
	month = {01/2014},
	publisher = {IEEE},
	organization = {IEEE},
	address = {Singapore},
	abstract = {Single-Photon Avalanche Diodes (SPADs) are solid-state photo-detectors capable of detecting single photons by exploiting the avalanche effect that occurs in the breakdown of a p-n junction biased above breakdown voltage. By this effect, a SPAD translates an incoming photon to a macroscopic current pulse. These devices are currently used for building medical devices characterized by a very high time resolution. An appealing application of SPAD is to use them as a basic block for building the entropy source of true random number generators. In this paper we focus on such application, and we explore the design challenges behind the realization of a quantum random number generator based on a massively parallel array of SPADs. The matrix under investigation comprises 512{\texttimes}128 independent cells that convert photons onto a raw bit-stream, which, as ensured by the properties of quantum physics, is characterized by a very high level of randomness. The sequences are read out in a 128-bit parallel bus, concatenated, and pipelined onto a de-biasing filter. Subsequently, we fabricated the proposed chip using a standard CMOS process. Our results, achieved on the manufactured device and coupling two matrices, show that our architecture can reach up to 5 Gbit/s while consuming 25pJ/bit, thus demonstrating scalability and performance for any random number generators based on SPADs},
	keywords = {quantum physics, random number generators, SPAD},
	isbn = {978-1-4799-2816-3},
	url = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6736726},
	author = {Regazzoni, Francesco and Burri, Samuel and Stucki, Damien and Maruyama, Yuki and Bruschini, Claudio and Charbon, Edoardo}
}
@article {18059,
	title = {Stealthy Dopant-Level Hardware Trojans: Extended Version},
	journal = {Journal of Cryptographic Engineering},
	volume = {4},
	issue = {1},
	year = {2014},
	month = {04/2014},
	pages = {19-31},
	abstract = {In recent years, hardware Trojans have drawn the attention of governments and industry as well as the scientific community. One of the main concerns is that integrated circuits, e.g., for military or critical-infrastructure applications, could be maliciously manipulated during the manufacturing process, which often takes place abroad. However, since there have been no reported hardware Trojans in practice yet, little is known about how such a Trojan would look like and how difficult it would be in practice to implement one. In this paper we propose an extremely stealthy approach for implementing hardware Trojans below the gate level, and we evaluate their impact on the security of the target device. Instead of adding additional circuitry to the target design, we insert our hardware Trojans by changing the dopant polarity of existing transistors. Since the modified circuit appears legitimate on all wiring layers (including all metal and polysilicon), our family of Trojans is resistant to most detection techniques, including fine-grain optical inspection and checking against {\textquotedblleft}golden chips{\textquotedblright}. We demonstrate the effectiveness of our approach by inserting Trojans into two designs{\textemdash}a digital post-processing derived from Intel{\textquoteright}s cryptographically secure RNG design used in the Ivy Bridge processors and a side-channel resistant SBox implementation{\textemdash}and by exploring their detectability and their effects on security.},
	keywords = {Hardware Trojans, Layout modifications, Malicious hardware, Trojan side-channel},
	issn = {2190-8516},
	doi = {10.1007/s13389-013-0068-0},
	author = {Becker, Georg and Regazzoni, Francesco and Paar, Christof and Burleson, Wayne}
}
@conference {18047,
	title = {Time of Flight Error Compensation for In-Tunnel Vehicle Localization},
	booktitle = {The Fourth International Workshop on Pervasive Networks for Emergency Management, 2014 (PerNEM{\textquoteright}14)},
	year = {2014},
	month = {03/2014},
	publisher = {IEEE},
	organization = {IEEE},
	address = {Budapest, Hungary},
	keywords = {calibration, position estimation, time of flight, vehicle localization, wireless sensor networks},
	doi = {10.1109/PerComW.2014.6815226},
	author = {Bala{\'c}, Katarina and Di Giulio, Pablo Andres and Taddeo, Antonio Vincenzo and Prevostini, Mauro}
}
@conference {17578,
	title = {An Algorithm for Extended Dynamic Range Video in Embedded Systems},
	booktitle = {SENSORNETS 2013 - 2nd International Conference on Sensor Networks},
	year = {2013},
	month = {02/2013},
	publisher = {INSTICC},
	organization = {INSTICC},
	address = {Barcelona, Spain},
	keywords = {embedded systems, extended dynamic range, HDR, image processing, sensor, videocamera},
	author = {Ferrante, Alberto and Chelodi, Massimo and Bruschi, Francesco and Mozzetti, Valeria}
}
@article {18060,
	title = {Automatic Application of Power Analysis Countermeasures},
	journal = {IEEE Transactions on Computers},
	volume = {PP},
	issue = {99},
	year = {2013},
	month = {12/2013},
	abstract = {We introduce a compiler that automatically inserts software countermeasures to protect cryptographic algorithms against power-based side-channel attacks. The compiler first estimates which instruction instances leak the most information through side-channels. This information is obtained either by dynamic analysis, evaluating an information theoretic metric over the power traces acquired during the execution of the input program, or by static analysis. As information leakage implies a loss of security, the compiler then identifies (groups of) instruction instances to protect with a software countermeasure such as random precharging or Boolean masking. As software protection incurs significant overhead in terms of cryptosystem runtime and memory usage, the compiler protects the minimum number of instruction instances to achieve a desired level of security. The compiler is evaluated on two block ciphers, AES and Clefia; our experiments demonstrate that the compiler can automatically identify and protect the most important instruction instances. To date, these software countermeasures have been inserted manually by security experts, who are not necessarily the main cryptosystem developers. Our compiler offers significant productivity gains for cryptosystem developers who wish to protect their implementations from side-channel attacks.},
	issn = {0018-9340},
	doi = {10.1109/TC.2013.219},
	author = {Bayrak, Ali Galip and Regazzoni, Francesco and Novo Bruna, David and Brisk, Philip and Standaert, Fran{\c c}ois-Xavier and Ienne, Paolo}
}
@conference {17741,
	title = {Calibration and in-Field Validation Tests of a Web-based Adaptive Management System for Monitoring - Scaphoideus titanus},
	booktitle = {Future Integrated Pest Management in Europe},
	year = {2013},
	abstract = {We developed a Web-based Adaptive Management System (WAMS) within a research project, called "SMART VINEYARD", which was funded by the Swiss Federal Commission for Technology and Innovation (Project 11307.1 PFES-ES). Goal of the project was to address the challenge of proposing a decision support system to provide real-time forecast of the life stages of - Scaphoideus titanus, vector of flavescence dor{\'e}e. The benefit of using the WAMS is to decide the timing of insecticide application and the planning of in-field monitoring tasks.},
	author = {Prevostini, Mauro and Taddeo, Antonio Vincenzo and Bala{\'c}, Katarina and Jermini, Mauro and Linder, Christian}
}
@conference {17768,
	title = {Characterization of In-tunnel Distance Measurements for Vehicle Localization},
	booktitle = {IEEE Wireless Communications and Networking Conference (WCNC)},
	year = {2013},
	address = {Shanghai, P.R. China},
	abstract = {An increased number of vehicular applications and services requires accurate distance measurements. Due to specific properties of radio waves propagation, it may not be effective to use ranging systems designed for other environments inside tunnels. In this paper we analysed the characteristics of time of flight based ranging for in-tunnel applications. Based on our analysis, we designed a vehicle localization system showing that the time of flight approach is a suitable, accurate and cost effective solution for this purpose. We designed and validated our solution by performing real experiments in a tunnel located in Lugano, Switzerland.},
	author = {Widmann, Daniel and Bala{\'c}, Katarina and Taddeo, Antonio Vincenzo and Prevostini, Mauro and Puiatti, Alessandro}
}
@conference {18069,
	title = {Comparison of Two Cameras based on Single Photon Avalanche Diodes (SPADS) for Fluorescence Lifetime Imaging Application with Picosecond Resolution},
	booktitle = {International Image Sensor Workshop (IISW)},
	year = {2013},
	month = {June},
	address = {Snowbird Resort, Utah, USA},
	author = {Powolny, Fran{\c c}ois and Burri, Samuel and Bruschini, Claudio and Michalet, Xavier and Regazzoni, Francesco and Charbon, Edoardo}
}
@conference {18072,
	title = {An eda-friendly protection scheme against side-channel attacks},
	booktitle = {Design, Automation and Test in Europe (DATE)},
	year = {2013},
	month = {March},
	address = {Grenoble, France},
	author = {Bayrak, Ali Galip and Velickovic, Nikola and Regazzoni, Francesco and Novo Bruna, David and Brisk, Philip and Ienne, Paolo}
}
@article {18061,
	title = {A Fast ULV Logic Synthesis Flow in Many-Vt CMOS Processes for Minimum Energy under Timing Constraints},
	journal = {IEEE Transactions on Circuits and Systems II},
	volume = {59},
	issue = {12},
	year = {2013},
	pages = {947-951},
	abstract = {Ultra-low-voltage (ULV) logic offers the opportunity to operate at the minimum-energy point (MEP) for applications with low-to-medium speed requirements. Unfortunately, the critical design constraint of achieving a reliable timing closure at the target frequency of the application becomes very complex in the wide design space of ULV including supply (Vdd) and threshold (Vt) voltage selection as well as netlist optimizations from the synthesis. In this paper, we propose a fast synthesis flow to accurately predict the Vdd/Vt MEP under strict timing constraints. Compared to an exhaustive search for the MEP under timing constraints based on numerous library recharacterizations and synthesis steps for all Vdd/Vt pairs, the proposed ULV flow dramatically speeds up the design process. Indeed, it requires a single library recharacterization and only three synthesis steps. Results obtained for several ITC{\textquoteright}99 benchmarks under a wide range of timing constraints from 0.1 to 30 MHz in 65-nm LP/GP CMOS demonstrate that the proposed flow has a less than 10\% energy penalty with respect to the absolute MEP computed with an exhaustive search and energy savings enhanced up to 2.4{\texttimes} compared to a conventional flow with Vdd scaling only.},
	issn = {1549-7747},
	doi = {10.1109/TCSII.2012.2231034},
	author = {Bol, David and Hocquet, C{\'e}dric and Regazzoni, Francesco}
}
@conference {18068,
	title = {Jailbreak Imagers: Transforming a Single-Photon Image Sensor into a True Random Number Generator},
	booktitle = {International Image Sensor Workshop (IISW)},
	year = {2013},
	month = {June},
	address = {Snowbird Resort, Utah, USA},
	author = {Burri, Samuel and Stucki, Damien and Maruyama, Yuki and Bruschini, Claudio and Charbon, Edoardo and Regazzoni, Francesco}
}
@conference {18071,
	title = {Lightweight AES-Based Authenticated Encryption},
	booktitle = {Fast Software Encryption (FSE)},
	year = {2013},
	month = {March},
	address = {Singapore},
	author = {Bogdanov, Andrey and Mendel, Florian and Regazzoni, Francesco and Rijmen, Vincent and Tischhauser, Elmar}
}
@conference {18090,
	title = {Run-time Optimization of a Dynamically Reconfigurable Embedded System Through Performance Prediction},
	booktitle = {23rd International Conference on Field Programmable Logic and Applications (FPL)},
	year = {2013},
	month = {09/2013},
	publisher = {IEEE},
	organization = {IEEE},
	address = {Porto, Portugal},
	doi = {10.1109/FPL.2013.6645523},
	author = {Mariani, Giovanni and Sima, Vlad-Mihai and Palermo, Gianluca and Zaccaria, Vittorio and Marchiori, Giacomo and Silvano, Cristina and Bertels, Koen}
}
@inbook {17996,
	title = {Self-Organizing Real-Time Services in Mobile Ad Hoc Networks},
	booktitle = {Self-Organization in Embedded Real-Time Systems},
	year = {2013},
	pages = {55-74},
	publisher = {Springer New York},
	organization = {Springer New York},
	isbn = {978-1-4614-1968-6},
	doi = {10.1007/978-1-4614-1969-3_3},
	url = {http://dx.doi.org/10.1007/978-1-4614-1969-3_3},
	author = {Kakuda, Yoshiaki and Ohta, Tomoyuki and Malek, Miroslaw},
	editor = {Higuera-Toledano, Teresa and Brinkschulte, Uwe and Rettberg, Achim}
}
@conference {18066,
	title = {Sleuth: Automated Verification of Software Power Analysis Countermeasures},
	booktitle = {Workshop on Cryptographic Hardware and Embedded Systems (CHES)},
	year = {2013},
	month = {August},
	address = {Santa Barbara, California, USA},
	author = {Bayrak, Ali Galip and Regazzoni, Francesco and Novo Bruna, David and Ienne, Paolo}
}
@conference {18067,
	title = {Stealthy Dopant-Level Hardware Trojans},
	booktitle = {Workshop on Cryptographic Hardware and Embedded Systems (CHES)},
	year = {2013},
	month = {August},
	address = {Santa Barbara, California, USA},
	author = {Becker, Georg and Regazzoni, Francesco and Paar, Christof and Burleson, Wayne}
}
@conference {18073,
	title = {Compact Implementation and Performance Evaluation of Hash Functions in ATtiny Devices},
	booktitle = {11th Smart Card Research and Advanced Application Conference (CARDIS)},
	year = {2012},
	month = {November},
	address = {Graz, Austria},
	author = {Balasch, Josep and Ege, Baris and Eisenbarth, Thomas and Grard, Benot and Gong, Zheng and Gneysu, Tim and Heyse, Stefan and Kerckhof, St{\'e}phanie and Koeune, Francois and Plos, Thomas and Poppelmann, Thomas and Regazzoni, Francesco and Standaert, Fran{\c c}ois-Xavier and Van Assche, Gilles and Van Keer, Ronny and Oldenzeel, Loic Van Oldene and von Maurich, Ingo}
}
@article {18491,
	title = {A Fast ULV Logic Synthesis Flow in Many-Vt CMOS Processes for Minimum Energy Under Timing Constraints},
	journal = {IEEE Transactions on Circuits and Systems II: Express Briefs  },
	volume = {59-II},
	issue = {12},
	year = {2012},
	month = {02/2012},
	pages = {947-951},
	type = {journal},
	chapter = {947},
	abstract = {Ultra-low-voltage (ULV) logic offers the opportunity to operate at the minimum-energy point (MEP) for applications with low-to-medium speed requirements. Unfortunately, the critical design constraint of achieving a reliable timing closure at the target frequency of the application becomes very complex in the wide design space of ULV including supply (Vdd) and threshold (Vt) voltage selection as well as netlist optimizations from the synthesis. In this paper, we propose a fast synthesis flow to accurately predict the Vdd/Vt MEP under strict timing constraints. Compared to an exhaustive search for the MEP under timing constraints based on numerous library recharacterizations and synthesis steps for all Vdd/Vt pairs, the proposed ULV flow dramatically speeds up the design process. Indeed, it requires a single library recharacterization and only three synthesis steps. Results obtained for several ITC{\textquoteright}99 benchmarks under a wide range of timing constraints from 0.1 to 30 MHz in 65-nm LP/GP CMOS demonstrate that the proposed flow has a less than 10\% energy penalty with respect to the absolute MEP computed with an exhaustive search and energy savings enhanced up to 2.4{\texttimes} compared to a conventional flow with Vdd scaling only},
	keywords = {circuit optimisation, CMOS logic circuits, fast ULV logic synthesis flow, Low power electronics},
	issn = {1549-7747},
	doi = {10.1109/TCSII.2012.2231034},
	url = {http://dx.doi.org/10.1109/TCSII.2012.2231034},
	author = {Bol, David and Hocquet, C{\'e}dric and Regazzoni, Francesco}
}
@inbook {18062,
	title = {Interaction between Fault Attack Countermeasures and the Resistance against Power Analysis Attacks},
	booktitle = {Fault Analysis in Cryptography},
	series = {Information Security and Cryptography Series, Springer},
	year = {2012},
	pages = {257-272},
	publisher = {Springer Berlin Heidelberg},
	organization = {Springer Berlin Heidelberg},
	abstract = {Most of the countermeasures against fault attacks on cryptographic systems that have been developed so far are based on the addition of information redundancy. While these countermeasures have been evaluated with respect to their cost (implementation overhead) and efficiency (fault coverage), little attention has been devoted to the question of the impact their use has on the effectiveness of other types of side-channel attacks, in particular, power analysis attacks. This chapter presents an experimental study whose goal is to determine whether the added information redundancy can increase the vulnerability of a cryptographic circuit to power analysis attacks.},
	isbn = {978-3-642-29656-7},
	doi = {10.1007/978-3-642-29656-7_15},
	author = {Regazzoni, Francesco and Breveglieri, Luca and Ienne, Paolo and Koren, Israel},
	editor = {Joye, Marc and Tunstall, Michael}
}
@conference {18074,
	title = {Simulation-Time Security Margin Assessment against power-based Side Channel Attacks},
	booktitle = {7th Workshop on Embedded Systems Security (WESS)},
	year = {2012},
	month = {October},
	address = {Tampere, Finland},
	author = {Barenghi, Alessandro and Pelosi, Gerardo and Regazzoni, Francesco}
}
@conference {158.mariani2012date,
	title = {Using Multi-objective Design Space Exploration to Enable Run-time Resource Management for Reconfigurable Architectures},
	booktitle = {Proc. Design, Automation Test in Europe Conf. Exhibition (DATE)},
	year = {2012},
	month = {March},
	author = {Mariani, Giovanni and Sima, Vlad-Mihai and Palermo, Gianluca and Zaccaria, Vittorio and Silvano, Cristina and Bertels, Koen}
}
@inbook {141.aetherinbook.2011,
	title = {AETHER: Self-Adaptive Networked Entities: Autonomous Computing Elements for Future Pervasive Applications and Technologies},
	booktitle = {Reconfigurable Computing: From FPGAs to Hardware/Software Codesign},
	year = {2011},
	pages = {149{\textendash}184},
	publisher = {Springer},
	organization = {Springer},
	address = {New York, USA},
	abstract = {The AETHER project has laid the foundation of a complete new framework for designing and programming computing resources that live in changing environments and need to re-configure their objectives in a dynamic way. This chapter contributes to a strategic research agenda in the field of self-adaptive computing systems. It brings inputs to the reconfigurable hardware community and proposes directions to go for reconfigurable hardware and research on self-adaptive computing; it tries to identify some of the most promising future technologies for reconfiguration, while pointing out the main foreseen Challenges for reconfigurable hardware. This chapter presents the main solutions the AETHER project proposed for some of the major concerns in trying to engineer a self-adaptive computing system. The text exposes the AETHER vision of self-adaptation and its requirements. It describes and discusses the proposed solutions for tackling self-adaptivity at the various levels of abstractions. It exposes how the developed technologies could be put together in a real methodology and how self-adaptation could then be used in potential applications. Finally and based on lessons learned from AETHER, we discuss open issues and research opportunities and put those in perspective along other investigations and roadmaps.},
	isbn = {978-1-4614-0061-5},
	author = {Gamrat, Christian and Philippe, Jean-Marc and Jesshope, Chris and Shafarenko, Alex and Bisdounis, Labros and Bondi, Umberto and Ferrante, Alberto and Cabestany, Joan and Huebner, Michael and Parsinnen, Juha and Kadlec, Jiri and Danek, Martin and Tain, Benoit and Eisenbach, Susan and Auguin, Michel and Diguet, Jean-Philippe and Lenormand, Eric and Roux, Jean-Luc},
	editor = {Cardoso, Joao Manuel Pai and Huebner, Michael}
}
@inbook {140.KaTuPaSiZaMaBoDo.2011,
	title = {Design Space Exploration of Parallel Architectures},
	booktitle = {Multi-objective design space exploration of multiprocessor SoC architectures: the MULTICUBE approach},
	year = {2011},
	publisher = {Springer},
	organization = {Springer},
	address = {New York, USA},
	abstract = {This chapter will present two significant applications of the MULTICUBE design space exploration framework. The first part will present the design space exploration of a low power processor developed by STMicroelectronics by using the modeFRONTIER tool to demonstrate the benefits DSE not only in terms of objective quality, but also in terms of impact on the design process within the corporate environment. The second part will describe the application of RSM models developed within MULTICUBE to a tiled, multiple-instruction, many-core architecture developed by ICT China. Overall, the results have showed that different models can present a trade-off of accuracy versus computational effort. In fact, throughout the evaluation, we observed that high accuracy models require high computational time (for both model construction time and prediction time); vice-versa low model construction and prediction time has led to low accuracy.},
	author = {Kavka, Carlos and Turco, Alessandro and Palermo, Gianluca and Silvano, Cristina and Zaccaria, Vittorio and Mariani, Giovanni and Bocchio, Sara and Dongrui, Fan}
}
@conference {154.BaChDe11.ISWCS,
	title = {Energy-Throughput Simulation Approach for Heterogeneous LTE scenarios},
	booktitle = {ISWCS{\textquoteright}11: Proceedings of The Eighth International Symposium on Wireless Communication Systems},
	year = {2011},
	month = {November 6-9},
	pages = {1{\textendash}5},
	address = {Aachen, Germany},
	abstract = {In order to increase overall LTE system performance femtocells have been proposed as a user-based solution promising to give much better service to the user specially indoor. Their deployment should improve the total system capacity noticeably and decrease drastically the power consumption. On the other hand these small indoor cells make the network planning strategies much more complex given the uncertainty of their position and their load; femtocells are after all managed by the users. Goal of this work is to provide a simulation approach to determine the effects of heterogeneous cell deployment on the performance of an LTE network. The simulation framework allows to realistically compare the power consumption and throughput of the overall system. The key components are the combination of indoor and outdoor propagation modeling, and the diversification of femto, micro and macro-cell energy consumption models. The model further contains complex city-like building structures, multiple communication layers (eNodeBs and femtocells) distributed over a three-dimensional map and numerous users moving across different areas while adapting their service requirements. The simulation approach results in relatively computationally inexpensive simulations and allows to model the expected throughput and energy consumption for various heterogeneous LTE scenarios.},
	keywords = {long term evolution (LTE)},
	doi = {http://dx.doi.org/10.1109/ISWCS.2011.6125377},
	author = {Baddour, Rami and Chiumento, Alessandro and Desset, Claude}
}
@conference {18079,
	title = {Exploring the Feasibility of Low Cost Fault Injection Attacks on Sub-Threshold Devices through an Example of a 65nm AES Implementation},
	booktitle = {7th Workshop on RFID Security and Privacy (RFIDSec)},
	year = {2011},
	month = {June},
	address = {Amherst, Massachussets, USA},
	author = {Barenghi, Alessandro and Hocquet, C{\'e}dric and Bol, David and Standaert, Fran{\c c}ois-Xavier and Regazzoni, Francesco and Koren, Israel}
}
@conference {18080,
	title = {A First Step Towards Automatic Application of Power Analysis Countermeasures},
	booktitle = {48th Design Automation Conference (DAC)},
	year = {2011},
	month = {June},
	address = {San Diego, Califorina},
	author = {Bayrak, Ali Galip and Regazzoni, Francesco and Brisk, Philip and Standaert, Fran{\c c}ois-Xavier and Ienne, Paolo}
}
@article {18063,
	title = {Harvesting the potential of nano-CMOS for lightweight cryptography: An ultra-low-voltage 65 nm AES coprocessor for passive RFID tags},
	journal = {Springer Journal of Cryptographic Engineering},
	volume = {1},
	issue = {1},
	year = {2011},
	author = {Hocquet, C{\'e}dric and Kamel, Dina and Regazzoni, Francesco and Legat, Jean-Didier and Flandre, Denis and Bol, David and Standaert, Fran{\c c}ois-Xavier}
}
@inbook {17734,
	title = {The MULTICUBE Design Flow},
	booktitle = {Multi-objective Design Space Exploration of Multiprocessor SoC Architectures},
	year = {2011},
	pages = {3-17},
	publisher = {Springer New York},
	organization = {Springer New York},
	isbn = {978-1-4419-8836-2},
	doi = {10.1007/978-1-4419-8837-9_1},
	url = {http://dx.doi.org/10.1007/978-1-4419-8837-9_1},
	author = {Silvano, Cristina and Fornaciari, William and Palermo, Gianluca and Zaccaria, Vittorio and Castro, Fabrizio and Martinez, Marcos and Bocchio, Sara and Zafalon, Roberto and Avasare, Prabhat and Vanmeerbeeck, Geert and Ykman-Couvreur, Chantal and Wouters, Maryse and Kavka, Carlos and Onesti, Luka and Turco, Alessandro and Bondi, Umberto and Mariani, Giovanni and Posadas, Hector and Villar, Eugenio and Wu, Chris and Dongrui, Fan and Hao, Zhang},
	editor = {Silvano, Cristina and Fornaciari, William and Villar, Eugenio}
}
@inbook {139.Sietal2.2011,
	title = {MULTICUBE: Multi-Objective Design Space Exploration of Multi-Core Architectures},
	booktitle = {VLSI 2010 Annual Symposium},
	volume = {105},
	year = {2011},
	pages = {47-63},
	publisher = {Springer},
	organization = {Springer},
	address = {Netherlands},
	abstract = {Given the increasing complexity of Chip Multi-Processors (CMPs), a wide range of architecture parameters must be explored at design time to find the best trade-off in terms of multiple competing objectives (such as energy, delay, bandwidth, area, etc.) The design space of the target architectures is huge because it should consider all possible combinations of each hardware parameter (e.g., number of processors, processor issue width, L1 and L2 cache sizes, etc.). In this complex scenario, intuition and past experience of design architects is no more a sufficient condition to converge to an optimal design of the system. Indeed, Automatic Design Space Exploration (DSE) is needed to systematically support the analysis and quantitative comparison of a large amount of design alternatives in terms of multiple competing objectives (by means of Pareto analysis). The main goal of the MULTICUBE project consists of the definition of an automatic Design Space Exploration framework to support the design of next generation many-core architectures.},
	isbn = {978-94-007-1487-8},
	url = {http://dx.doi.org/10.1007/978-94-007-1488-5_4},
	author = {Silvano, Cristina and Fornaciari, William and Palermo, Gianluca and Zaccaria, Vittorio and Castro, Fabrizio and Martinez, Marcos and Bocchio, Sara and Zafalon, Roberto and Avasare, Prabhat and Vanmeerbeeck, Geert and Ykman-Couvreur, Chantal and Wouters, Maryse and Kavka, Carlos and Onesti, Luka and Turco, Alessandro and Bondi, Umberto and Mariani, Giovanni and Posadas, Hector and Villar, Eugenio and Wu, Chris and Dongrui, Fan and Hao, Zhang and Shibin, Tang}
}
@conference {18081,
	title = {Power-Gated MOS Current Mode Logic (PG-MCML): A Power-Aware DPA-Resistant Standard Cell Library},
	booktitle = {48th Design Automation Conference (DAC)},
	year = {2011},
	month = {June},
	address = {San Diego, Califorina},
	author = {Cevrero, Alessandro and Regazzoni, Francesco and Schwander, Michael and Badel, St{\'e}phane and Ienne, Paolo and Leblebici, Yusuf}
}
@conference {17694,
	title = {WAMS - an adaptive system for knowledge acquisition and decision support: the case of Scaphoideus titanus},
	booktitle = {IOBC/WPRS European Meeting},
	year = {2011},
	month = {10/2011},
	pages = {57-64},
	publisher = {Working Group on Integrated Protection and Production in Viticulture},
	organization = {Working Group on Integrated Protection and Production in Viticulture},
	address = {Lacanau, France},
	author = {Prevostini, Mauro and Taddeo, Antonio Vincenzo and Bala{\'c}, Katarina and Rigamonti, Ivo and Baumg{\"a}rtner, Johann and Jermini, Mauro}
}
@conference {124.LuKaBo10,
	title = {Adopting system engineering methodology to Virtual Power Systems design flow},
	booktitle = {CPSWEEK/GREEMBED 2010: Proceedings of the First Workshop on Green and Smart Embedded System Technology: Infrastructures, Methods and Tools},
	year = {2010},
	month = {April},
	address = {Stockholm, Sweden},
	abstract = {The concept of Virtual Power System (VPS) emerges as a promising response for increased concerns on secure, sustainable and at the same time {\textquoteright}clean{\textquoteright} energy supply requests. This novel concept aims at boosting operational efficiency of Distributed Energy Resources (DER) but also at establishing them as an autonomous commercial actor on the open energy market. Nevertheless, VPSs are fairly complex HW/SW systems that require holistic multidisciplinary approach and also novel specification, modeling and analysis instruments to facilitate mutual understanding among stakeholders from different fields. We introduce UML/SysML based modeling methodology to describe such power system related issues aiming at providing an unified modeling instrument applicable for VPSs design flow. In the proposed system engineering methodology, system representation starts from a very general context description and gets refined through different levels of abstraction down to concrete embedded systems employed to perform defined tasks.},
	author = {Lukovi{\'c}, Slobodan and Kaitovi{\'c}, Igor and Bondi, Umberto}
}
@conference {126.MaPaZaBrJoSi11,
	title = {A Correlation-based Design Space Exploration Methodology for Multi-Processor Systems-on-Chip},
	booktitle = {Proceedings of DAC 2010: Design Automation Conference},
	year = {2010},
	month = {June},
	pages = {120{\textendash}125},
	address = {Anheim, CA, USA},
	abstract = {Given the increasing complexity of multi-processor systems-on-chip, a wide range of parameters must be tuned to find the best trade-offs in terms of the selected system figures of merit (such as energy, delay and area). This optimization phase is called Design Space Exploration (DSE) consisting of a Multi-Objective Optimization (MOO) problem. In this paper, we propose an iterative design space exploration methodology exploiting the statistical properties of known system configurations to infer, by means of a correlation-based analysis, the next design points to be analyzed with low-level simulations. In fact, the knowledge of few design points is used to predict the expected improvement of unknown configurations. We show that the correlation of the configurations within the multi-processor design space can be modeled successfully with analytical functions and, thus, speed up the overall exploration phase. This makes the proposed methodology a model-assisted heuristic that, for the first time, exploits the correlation about architectural configurations to converge to the solution of the multi-objective problem.},
	keywords = {design space exploration, kriging, multiprocessor system-on-chip (MPSoC), response surface},
	author = {Mariani, Giovanni and Palermo, Gianluca and Zaccaria, Vittorio and Brankovic, Aleksandar and Jovic, Jovana and Silvano, Cristina}
}
@conference {130.LuKaMuBoKuPo10,
	title = {Functional model of Virtual Power Plant (VPP)},
	booktitle = {Proceedings of the 2010 CIGRE (International Council on Large Electric Systems) Session},
	year = {2010},
	month = {July},
	address = {Paris, France},
	keywords = {smart grid, unified modeling language (UML), virtual power plants},
	author = {Lukovi{\'c}, Slobodan and Kaitovi{\'c}, Igor and Mura, Marcello and Bondi, Umberto and Kuli{\'c}, Filip and Popovi{\'c}, Dragan}
}
@conference {18087,
	title = {Low Cost Software Countermeasures Against Fault Attacks: Implementation and Performances Trade Offs},
	booktitle = {5th Workshop on Embedded Systems Security (WESS)},
	year = {2010},
	month = {October},
	address = {Scottsdale, Arizona, USA},
	author = {Barenghi, Alessandro and Breveglieri, Luca and Koren, Israel and Pelosi, Gerardo and Regazzoni, Francesco}
}
@conference {129.Sietal.ISVLSI11,
	title = {Multicube: Multi-objective design space exploration of multi-core architectures},
	booktitle = {ISVLSI 2010: IEEE Annual Symposium on VLSI},
	year = {2010},
	month = {July},
	pages = {488{\textendash}493},
	address = {Lixouri, Kefalonia - Greece},
	abstract = {Technology trends enable the integration of many processor cores in a System-on-Chip (SoC). In these complex architectures, several architectural parameters can be tuned to find the best trade-off in terms of multiple metrics such as energy and delay. The main goal of the MULTICUBE project consists of the definition of an automatic Design Space Exploration framework to support the design of next generation many-core architectures.},
	doi = {http://dx.doi.org/10.1109/ISVLSI.2010.67},
	author = {Silvano, Cristina and Fornaciari, William and Palermo, Gianluca and Zaccaria, Vittorio and Castro, Fabrizio and Martinez, Marcos and Bocchio, Sara and Zafalon, Roberto and Avasare, Prabhat and Vanmeerbeeck, Geert and Ykman-Couvreur, Chantal and Wouters, Maryse and Kavka, Carlos and Onesti, Luka and Turco, Alessandro and Bondi, Umberto and Mariani, Giovanni and Posadas, Hector and Villar, Eugenio and Wu, Chris and Dongrui, Fan and Hao, Zhang and Shibin, Tang}
}
@conference {112.LuKaMuBo10,
	title = {Virtual Power Plant as a bridge between Distributed Energy Resources and Smart Grid},
	booktitle = {Proceedings of 43th Hawaii International Conference on System Sciences (HICSS{\textquoteright}43)},
	year = {2010},
	month = {January},
	address = {Hawaii, USA},
	abstract = {The liberalization of energy markets, especially in correlation with the Smart Grid concept development, requires adjusted legislation, new business models, energy stock exchanges establishment and many other advanced instruments. Realization of these features necessitates novel concepts to support such changes in the power system while granting security and reliability of supply. Such evolution poses new challenges to ICT (Information and Communication Technologies) to bridge the gap between increased complexity of deregulated market and on the other side expected rapid growth of number of players in power systems. Increasing presence of Distributed Energy Resources (DER) implementations constitutes a further source of complexity. Bearing in mind ongoing and possible scenarios we aim to determinate the place and role of the novel Virtual Power Plants (VPP) concept, related to the Smart Grid structure. At the same time we introduce an innovative modeling approach as an instrument to determine actors and highlight their actual roles and interactions from different point of view, trying to pave the way for development of a common understanding platform for variety of stakeholders. The effectiveness of the proposed modeling concept is shown through a number of UML models representing system level description of VPP at different levels of abstraction.},
	keywords = {distributed energy resources, smart grid, unified modeling language (UML), virtual power plants},
	doi = {http://dx.doi.org/10.1109/HICSS.2010.437},
	author = {Lukovi{\'c}, Slobodan and Kaitovi{\'c}, Igor and Mura, Marcello and Bondi, Umberto}
}
@article {18492,
	title = {Breaking ECC2K-130},
	journal = {IACR Cryptology ePrint Archive},
	volume = {2009},
	year = {2009},
	month = {11/2009},
	pages = {541},
	abstract = {Elliptic-curve cryptography is becoming the standard public-key primitive not only for mobile devices but also for high-security applications. Advantages are the higher cryptographic strength per bit in comparison with RSA and the higher speed in implementations. To improve understanding of the exact strength of the elliptic-curve discrete-logarithm problem, Certicom has published a series of challenges. This paper describes breaking the ECC2K-130 challenge using a parallelized version of Pollard{\textquoteright}s rho method. This is a major computation bringing together the contributions of several clusters of conventional computers, PlayStation~3 clusters, computers with powerful graphics cards and FPGAs. We also give /preseestimates for an ASIC design. In particular we present * our choice and analysis of the iteration function for the rho method; * our choice of finite field arithmetic and representation; * detailed descriptions of the implementations on a multitude of platforms: CPUs, Cells, GPUs, FPGAs, and ASICs; * details about running the attack. },
	keywords = {Attacks, automorphisms, binary fields, Certicom challenges, DLP, ECC, implementation, Koblitz curves, parallelized Pollard rho},
	url = {http://eprint.iacr.org/2009/541},
	author = {Bailey, Daniel V. and Batina, Lejla and Bernstein, Daniel J. and Birkner, Peter and Bos, Joppe W. and Chen, Hsieh - Chung and Cheng, Chen - Mou and van Damme, Gauthier and G{\"u}neysu, Tim and Gurkaynak, Frank and Kleinjung, Thorsten and Paar, Christof and Regazzoni, Francesco and Niederhagen, Ruben and Schwabe, Peter and Uhsadel, Leif and Van Herrewege, Anthony}
}
@conference {18084,
	title = {The Certicom Challenges ECC2-X},
	booktitle = {Workshop on Special Purpose Hardware for Attacking Cryptographic Systems (SHARCS)},
	year = {2009},
	month = {September},
	address = {Lausanne, Switzerland},
	author = {Bailey, Daniel V. and Baldwin, Brian and Batina, Lejla and Bernstein, Daniel J. and Birkner, Peter and Bos, Joppe W. and van Damme, Gauthier and de Meulenaer, Giacomo and Fan, Junfeng and Gurkaynak, Frank and G{\"u}neys, Tim and Kleinjung, Thorsten and Lange, Tanja and Mentens, Nele and Paar, Christof and Regazzoni, Francesco and Schwabe, Peter and Uhsadel, Leif}
}
@conference {106.BoSa09,
	title = {Creating an Embedded Systems Program from Scratch: Nine years of experience at ALaRI},
	booktitle = {Proceedings of the 2009 Workshop on Embedded System Education},
	year = {2009},
	month = {October},
	address = {Grenoble, France},
	abstract = {In 1999, experts form academia and industry met in a workshop dealing with education in Embedded Systems Design: at the time there were no specifically oriented programs, and an {\textquoteright}ideal{\textquoteright} educational track was designed. One year later, that educational design was implemented with a one-year {\textquoteright}executive-type{\textquoteright} Master at Universit{\`a} della Svizzera italiana, in Switzerland; over the years, the program blossomed and extended, with development of a two-year Master of Science program as well. The experience is discussed here; results and perspectives are analyzed.},
	keywords = {education, embedded systems},
	doi = {http://dx.doi.org/10.1145/1719010.1719012},
	author = {Bondi, Umberto and Sami, Mariagiovanna}
}
@inbook {18085,
	title = {A Design Flow and Evaluation Framework for DPA-resistant Instruction Set Extensions},
	booktitle = {Cryptographic Hardware and Embedded Systems (CHES)},
	series = {Lecture Notes in Computer Science},
	volume = {5747},
	year = {2009},
	month = {September},
	pages = {205-219},
	publisher = {Springer Berlin Heidelberg},
	organization = {Springer Berlin Heidelberg},
	address = {Lausanne, Switzerland},
	abstract = {Power-based side channel attacks are a significant security risk, especially for embedded applications. To improve the security of such devices, protected logic styles have been proposed as an alternative to CMOS. However, they should only be used sparingly, since their area and power consumption are both significantly larger than for CMOS. We propose to augment a processor, realized in CMOS, with custom instruction set extensions, designed with security and performance as the primary objectives, that are realized in a protected logic. We have developed a design flow based on standard CAD tools that can automatically synthesize and place-and-route such hybrid designs. The flow is integrated into a simulation and evaluation environment to quantify the security achieved on a sound basis. Using MCML logic as a case study, we have explored different partitions of the PRESENT block cipher between protected and unprotected logic. This experiment illustrates the tradeoff between the type and amount of application-level functionality implemented in protected logic and the level of security achieved by the design. Our design approach and evaluation tools are generic and could be used to partition any algorithm using any protected logic style.},
	isbn = {978-3-642-04137-2},
	doi = {10.1007/978-3-642-04138-9_15},
	author = {Regazzoni, Francesco and Cevrero, Alessandro and Standaert, Fran{\c c}ois-Xavier and Badel, St{\'e}phane and Kluter, Theo and Brisk, Philip and Leblebici, Yusuf and Ienne, Paolo}
}
@conference {102.LuKaMuBo09,
	title = {Functional requirements of embedded systems for monitoring and control structure of Virtual Power Plants},
	booktitle = {Proceedings of the 2009 IEEE Workshop on Environmental, Energy, and Structural Monitoring Systems},
	year = {2009},
	month = {September},
	address = {Crema, Italy},
	abstract = {Efficient integration of distributed renewable generation into a reliable single entity in technical and commercial terms is one of key issues for successful realization of smart-grids. The novel concept of Virtual Power Plants (VPP) emerges to be promising response to these needs. ICT is the enabling technology for VPP implementation. In fact, an efficient monitoring and control system coupled with appropriate communication structure must be designed in a scalable and modular way so that full interoperability among components of the system is achieved. On top of that, Control Center applications take care of power flow optimization (production, consumption, ancillary services) and high-level applications (e.g. energy trading, Demand Side Management etc.). In this work we focus on functional requirements for realization of such concept by means of embedded systems.},
	keywords = {monitoring and control, system level modeling, virtual power plants},
	doi = {http://dx.doi.org/10.1109/EESMS.2009.5341320},
	author = {Lukovi{\'c}, Slobodan and Kaitovi{\'c}, Igor and Mura, Marcello and Bondi, Umberto}
}
@conference {97.Silvanoetal09,
	title = {MULTICUBE: Multi-Objective Design Space Exploration of Multiprocessor Architectures for Embedded Multimedia Applications},
	booktitle = {Proceedings of the DATE{\textquoteright}09 workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications},
	year = {2009},
	month = {April},
	address = {Nice, France},
	author = {Silvano, Cristina and Palermo, Gianluca and Zaccaria, Vittorio and Fornaciari, William and Zafalon, Roberto and Bocchio, Sara and Martinez, Marcos and Wouters, Maryse and Vanmeerbeeck, Geert and Avasare, Prabhat and Onesti, Luka and Kavka, Carlos and Bondi, Umberto and Mariani, Giovanni and Villar, Eugenio and Posadas, Hector and Wu, Chris and Dongrui, Fan and Hao, Zhang}
}
@conference {82.BeBrFaRe08,
	title = {A 640 Mbit/s 32-bit Pipelined Implementation of the AES Algorithm},
	booktitle = {SECRYPT},
	year = {2008},
	month = {July 26},
	address = {Porto, Portugal},
	abstract = {Due to the diffusion of cryptography in real time applications, performances in cipher and decipher operations are nowadays more important than in the past. On the other side, while facing the problem for embedded systems, additional constraints of area and power consumption must be considered. Many optimized software implementations, instruction set extensions and co-processors, were studied in the past with the aim to either increase performances or to keep the cost low. This paper presents a co-processor that aims to be an intermediate solution, suitable for such applications that require a throughput in the Megabit range and where the die size is a bit relaxed as constraint. To achieve this goal, the core is designed to operate at 32 bits and the throughput is guaranteed by a 2 stage pipeline with data forwarding. The obtained results synthesizing our coprocessor by means of the CMOS $0.18$ $μ$m standard cell library show that the throughput reaches 640 Mbit/s while the circuit size is of only 20 K equivalent gates. },
	keywords = {cryptography, security},
	author = {Bertoni, Guido Marco and Breveglieri, Luca and Farina, Roberto and Regazzoni, Francesco}
}
@conference {75.BoPaSa08,
	title = {An adaptable FPGA-based System for Regular Expression Matching},
	booktitle = {Proceedings of Design, Automation and Test in Europe (DATE) Conference},
	year = {2008},
	month = {March 10-14},
	address = {Munich, Germany},
	abstract = {In many applications string pattern matching is one of the most intensive tasks in terms of computation time and memory accesses. Network Intrusion Detection Systems and DNA Sequence Matching are two examples. Since software solutions are not able to satisfy the performance requirements, specialized hardware architectures are required. In this paper we propose a complete framework for regular expression matching, both in its architecture and compiler. This special-purpose processor is programmed using regular expressions as programming language. With the parallelism exploited in the design it is possible to achieve a throughput greater than one character per clock cycle, requiring O(n) memory space. The VHDL description of the proposed architecture is fully configurable. A design space exploration to find the optimal architecture based on area and performance cost-function is presented.},
	keywords = {FPGA-based design, regular expression matching},
	doi = {http://dx.doi.org/10.1109/DATE.2008.4484852},
	author = {Bonesana, Ivano and Paolieri, Marco and Santambrogio, Marco Domenico}
}
@conference {89.ReEiBrIeKo,
	title = {Can knowledge regarding the presence of countermeasures against fault attacks simplify power attacks on cryptographic devices?},
	booktitle = {Proceedings of 23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS 08)},
	year = {2008},
	month = {October 1-3},
	abstract = {Side-channel attacks are nowadays a serious concern when implementing cryptographic algorithms. Powerful ways for gaining information about the secret key as well as various countermeasures against such attacks have been recently developed. Although it is well known that such attacks can exploit information leaked from different sources, most prior works have only addressed the problem of protecting a cryptographic device against a single type of attack. Consequently, there is very little knowledge on how a scheme for protecting a device against one type of side-channel attack may affect its vulnerability to other types of side-channel attacks. In this paper we focus on devices that include protection against fault injection attacks (using different error detection schemes) and explore whether the presence of such fault detection circuits affects the resistance against attacks based on power analysis. Using the AES S-Box as an example, we performed attacks on the unprotected implementation as well as modified implementations with parity check circuits or residue check circuits (mod3 and mod7). In particular, we focus on the question whether the knowledge of the presence of error detection circuitry in the cryptographic device can help an attacker who attempts to mount a power attack on the device. Our results show that the presence of error detection circuitry helps the attacker even if he is unaware of this circuitry, and that the benefit to the attacker increases with the number of check bits used for the purpose of error detection.},
	author = {Regazzoni, Francesco and Eisenbarth, Thomas and Breveglieri, Luca and Ienne, Paolo and Koren, Israel}
}
@conference {67.ReEiGr07,
	title = {Power Attacks Resistance of Cryptographic S-boxes with added Error Detection Circuits},
	booktitle = {proceedings of: {\textquoteright}22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT{\textquoteright}07)},
	year = {2007},
	month = {September 26-28},
	address = {Rome, Italy},
	abstract = {Many side-channel attacks on implementations of cryptographic algorithms have been developed in recent years demonstrating the ease of extracting the secret key. In response, various schemes to protect cryptographic devices against such attacks have been devised and some implemented in practice. Almost all of these protection schemes target an individual side-channel attack and consequently, it is not obvious whether a scheme for protecting the device against one type of side-channel attacks may make the device more vulnerable to another type of side-channel attacks. We examine in this paper the possibility of such a negative impact for the case where fault detection circuitry is added to a device (to protect it against fault injection attacks) and analyze the resistance of the modified device to power attacks. To simplify the analysis we focus on only one component in the cryptographic device (namely, the S-box in the AES and Kasumi ciphers), and perform power attacks on the original implementation and on a modified implementation with an added parity check circuit. Our results show that the presence of the parity check circuitry has a negative impact on the resistance of the device to power analysis attacks.},
	keywords = {cryptography, fault tolerance, reliable applications, side channel attacks},
	author = {Regazzoni, Francesco and Eisenbarth, Thomas and Gro{\ss}sch{\"a}dl, Johann and Breveglieri, Luca and Ienne, Paolo and Koren, Israel and Paar, Christof}
}
@conference {65.GiTaVeBrKo07,
	title = {A Question Answering service for information retrieval in Cooper},
	booktitle = {COOPER Workshop in conjunction with EC-TEL07 Conference},
	year = {2007},
	month = {September 17},
	abstract = {In Cooper, part of the student support will be provided by a Question Answering application in the form of a webservice. Question Answering allows a user to use the content of project document as input to find related documents as well as related experts. Latent Semantic Analysis as an underlying technique is briefly discussed followed by a description of our Latent Semantic Analysis engine and the software architecture that was developed. Issues for further development are also mentioned. The final section contains a specific case study of an environment in which an implementation is planned.},
	keywords = {information retrieval, latent semantic analysis, question answering, singular value decomposition},
	author = {Giesbers, Bas and Taddeo, Antonio Vincenzo and Vegt, Wim and Bruggen, Jan and Koper, Rob}
}
@conference {70.PaBoSa07,
	title = {ReCPU: a Parallel and Pipelined Architecture for Regular Expression Matching},
	booktitle = {Proceedings of 15th Annual IFIP International Conference on Very Large Scale Integration {(IFIP-VLSI 07)},(best paper award)},
	year = {2007},
	month = {October 15-17},
	address = {Atlanta, Georgia, USA},
	abstract = {Text pattern matching is one of the main and most computation intensive parts of systems such as Network Intrusion Detection Systems and DNA Sequencing Matching. Soft- ware solutions to this are available but often they do not satisfy the requirements in terms of performance. This pa- per presents a new hardware approach for regular expression matching: ReCPU. The proposed solution is a parallel and pipelined architecture able to deal with the common regular expression semantics. This implementation based on several parallel units achieves a throughput of more than one char- acter per clock cycle (maximum performance of state of the art solutions) requiring just O(n) memory locations (where n is the length of the regular expression). Performance has been evaluated synthesizing the VHDL description. Area and time constraints have been analyzed. Experimental re- sults are obtained simulating the architecture.},
	doi = {http://dx.doi.org/10.1109/VLSISOC.2007.4402466},
	author = {Paolieri, Marco and Bonesana, Ivano and Santambrogio, Marco Domenico}
}
@conference {69.BoIoNeTaTo07,
	title = {Role Based Access Control for the interaction with Search Engines},
	booktitle = {COOPER Workshop in conjunction with EC-TEL07 Conference},
	year = {2007},
	month = {September 17},
	abstract = {Search engine-based features are a basic interaction mean for users to find information inside a Web-based Learning Management Systems (LMS); nonetheless, traditional solutions lack in mechanisms for access rights management for data contained in search engines{\textquoteright} indexes. This paper explores the integration of a Role Based Access Control (RBAC) mechanism for the interaction with a search engine in a Web-based LMS. We first outline a reference conceptual model for the design of Web-based LMSs exploiting RBAC by means of WebML, a visual modeling language for the high-level specification of data-intensive Web applications. Then, we propose a model-driven approach for the definition of a RBAC-driven interaction between users and search engines, extending WebML with new modeling primitives and outlining significative modeling patterns for the specification of the visibility and action access control levels.},
	keywords = {access control modeling, index modeling, search engine design, web engineering},
	author = {Bozzon, Alessandro and Iofciu, Tereza and Nejdl, Wolfgang and Taddeo, Antonio Vincenzo and Tonnies, Sascha}
}
@conference {59.ReBaEi07,
	title = {Simulation-based Methodology for Evaluating DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies},
	booktitle = {International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS IC 07)},
	year = {2007},
	month = {July 16-19},
	address = {Samos, Greece},
	abstract = {This paper explores the resistance of MOS Current Mode Logic (MCML) against Differential Power Analysis (DPA) attacks. Circuits implemented in MCML, in fact, have unique characteristics both in terms of power consumption and the dependency of the power profile from the input signal pattern. Therefore, MCML is suitable to protect cryptographic hardware from DPA and similar side-channel attacks. In order to demonstrate the effectiveness of different logic styles against power analysis attacks, the non-linear bijective function of the Kasumi algorithm (known as substitution box S7) was implemented with CMOS and MCML technology, and a set of attacks was performed using power traces derived from SPICE-level simulations. Although all keys were discovered for CMOS, only very few attacks to MCML were successful.},
	keywords = {current mode logic (CML), differential power analysis (DPA), power simulation, side channel attacks},
	author = {Regazzoni, Francesco and Badel, St{\'e}phane and Eisenbarth, Thomas and Gro{\ss}sch{\"a}dl, Johann and Poschmann, Axel and Toprak, Zeynep and Macchetti, Marco and Pozzi, Laura and Paar, Christof and Leblebici, Yusuf and Ienne, Paolo}
}
@conference {46.ReBoDjMa07,
	title = {Tairona, an Open Source Platform for Worldwide Meeting and Tutoring},
	booktitle = {World Conference on Educational Multimedia, Hypermedia and Telecommunications 7 (ED-MEDIA 07)},
	year = {2007},
	address = {Vancouver, Canada},
	abstract = {Tairona is a web-based platform for real time meeting and tutoring. It aims to provide a solution for face to face synchronous communication between the tutor and the students in remote faculties and similar environments where a life meeting in not possible. In particular the application is tailored on needs of a scenario that is very unique: in the considered institution in fact, teachers and students meet themselves only for the week necessary to complete the course. In this paper we present the requirements that led us to design and implement Taiorna.},
	keywords = {java, learning, remote application, voice over IP (VoIP)},
	author = {Regazzoni, Francesco and Bonesana, Ivano and Djakov, Maksim and Mattiuz, Amanda}
}
@conference {45.BoTa2006,
	title = {COOPER: Towards A Collaborative Open Environment of Project-centred Learning},
	booktitle = {proceedings to EC-TEL{\textquoteright}06 conference},
	year = {2006},
	month = {October 1-4},
	address = {Crete, Greece},
	abstract = {Nowadays, engineering studies are characterized by high mobility of students, lecturers and workforce and by the dynamics of multi-national companies where classes or students{\textquoteright} teams composed of persons with different competencies and backgrounds, working together in projects to solve complex problems. Such an environment will become increasingly relevant in multinational universities and companies, and it has brought a number of challenges to existing e-learning technologies. COOPER is an ongoing project that focuses on developing and testing such a collaborative and project-centred leaning environment. This paper proposes a COOPER framework and shows its approaches to address the various research challenges.},
	keywords = {project-centred learning, remote cooperation},
	author = {Bongio, Aldo and Bruggen, Jan and Ceri, Stefano and Cristea, Valentin and Dolog, Peter and Hoffmann, Andreas and Matera, Maristella and Mura, Marzia and Taddeo, Antonio Vincenzo and Zhou, Xuan and Zoni, Larissa}
}
@conference {39.1169233,
	title = {Speeding Up AES By Extending a 32 bit Processor Instruction Set},
	booktitle = {ASAP {\textquoteright}06: Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP{\textquoteright}06)},
	year = {2006},
	pages = {275-282},
	publisher = {IEEE Computer Society},
	organization = {IEEE Computer Society},
	address = {Washington, DC, USA},
	abstract = {Nowadays the need of speed in cipher and decipher operations is more important than in the past. This is due to the diffusion of real time applications, which fact involves the use of cryptography. Many co-processors for cryptography were studied and presented in the past, but only few works were addressed to the enhancement of the instruction set architecture (ISA) of the embedded processor. This paper presents an extension of the ISA of a 32 bit processor, that aims at speeding up the software implementations of the AES algorithm. After the identification of the most frequently executed and the most time consuming sections of the algorithm, a set of dedicated instructions is designed in order to improve the performances of the cipher operations. We validate our instruction set extension by measuring the speed up for different optimized implementations of AES using an ARM processor simulator, but the enhancements we propose are general enough to be applied to almost all 32 bit processors.},
	keywords = {cryptography, HW/SW co-design, instruction set extension},
	isbn = {0-7695-2682-9},
	doi = {http://dx.doi.org/10.1109/ASAP.2006.62},
	author = {Bertoni, Guido Marco and Breveglieri, Luca and Farina, Roberto and Regazzoni, Francesco}
}
@conference {34.BaLaPrevos2005,
	title = {Design and Synthesis of Reusable Platforms with Programmable Interconnects},
	booktitle = {UML-SoC 2005},
	year = {2005},
	month = {June 12},
	pages = {43-48},
	address = {Anaheim, California},
	abstract = {Platform based design requires to restrict the number of possible design choices in order to make it possible to come up with programmable solutions able to cope with the current complexity of System-On-Chip (SoC) designs. Nowadays there is a general consensus toward the fact that an effective Electronic System Level (ESL) design methodology must provide a specific support for platform specification, hardware/software partitioning and programmatic interfaces synthesis in order to allow designers to exploit the potentials of state-of-the-art technologies. In this work we present a methodology that leverages on UML for building new architectural platforms to be used to be used in the system design process. We show how our methodology can allow to reuse pre-designed platforms by adding new architectural components and by customizing their interconnections},
	keywords = {HW/SW co-design, system-on-chip (SoC), unified modeling language (UML)},
	author = {Basu, Ananda Shankar and Lajolo, Marcello and Prevostini, Mauro}
}
@inbook {30.BaLaPre2005,
	title = {A Methodology for Bridging the Gap between UML and Codesign},
	booktitle = {UML for SOC Design},
	year = {2005},
	pages = {119-146},
	publisher = {Springer},
	organization = {Springer},
	address = {Dordrecht, The Netherlands},
	abstract = {The Unified Modeling Language (UML) is getting more popular among system designers due to the need to raise the level of abstraction in system specifications. We present here a methodology that integrates UML specifications with a hardware/software codesign platform. This work aims to give a contribution toward SoC Design Automation starting from system level specification down to hardware/software partitioning and integration.},
	keywords = {HW/SW co-design, methodology, system specifications, unified modeling language (UML)},
	author = {Basu, Ananda Shankar and Lajolo, Marcello and Prevostini, Mauro},
	editor = {Martin, Grant and Muller, Wolfgang}
}
@conference {17.NegBon2004,
	title = {The ALaRI Intranet: a Remote Collaboration Platform for a Worldwide Learning and Research Network},
	booktitle = {World Conference on Educational Multimedia, Hypermedia and Telecommunications 04 (ED-MEDIA 04)},
	year = {2004},
	pages = {5042-5047},
	publisher = {AACE Press},
	organization = {AACE Press},
	address = {Lugano, Switzerland},
	abstract = {The ALaRI Intranet is a web-based remote learning, tutoring and collaboration platform that has been developed within the ANTITESYS project. ANTITESYS is a EU project involving some of the major academic and industrial institutions in Europe; its aim is to foster academic-industrial collaboration in the field of embedded systems whilst forming selected students by means of a one-year master program, held at the ALaRI institute sited in Lugano, Switzerland. What makes this scenario very unique lies in the roles played by the industrial and academic partners of ANTITESYS. The two sides contribute to the training of the master students in different ways, but both share the problem of integrating remote and face-to-face meetings with the students and with the other stakeholders. In this paper, we present the requirements gathering process and the design phase of the ALaRI Intranet, plus some details about its actual implementation and some initial usage figures.},
	keywords = {case study, remote cooperation},
	author = {Negri, Luca and Bondi, Umberto}
}
@conference {21.968073,
	title = {Efficient AES implementations for ARM based platforms},
	booktitle = {SAC {\textquoteright}04: Proceedings of the 2004 ACM symposium on Applied computing},
	year = {2004},
	pages = {841{\textendash}845},
	publisher = {ACM Press, New York, USA},
	organization = {ACM Press, New York, USA},
	address = {Nicosia, Cyprus},
	abstract = {The Advanced Encryption Standard (AES) contest, started by the U.S. National Institute of Standards and Technology (NIST), saw the Rijndael [13] algorithm as its winner [11]. Although the AES is fully defined in terms of functionality, it requires best exploitation of architectural parameters in order to reach the optimum performance on specific architectures. Our work concentrates on ARM cores [1] widely used in the embedded industry. Most promising implementation choices for the common ARM Instruction Set Architecture (ISA) are identified, and a new implementation for the linear mixing layer is proposed. The performance improvement over current implementations is demonstrated by a case study on the Intel StrongARM SA-1110 Microprocessor [2]. Further improvements based on exploitation of memory hierarchies are also described, and the corresponding performance figures are presented.},
	keywords = {advanced encryption standard (AES), ARM microprocessor, cache memories, code optimisation},
	isbn = {1-58113-812-1},
	doi = {http://doi.acm.org/10.1145/967900.968073},
	author = {Atasu, Kubilay and Breveglieri, Luca and Macchetti, Marco}
}
@Patent {22.pat20040228482PATENT,
	title = {Method of implementing one-to-one binary function and relative hardware device, especially for a Rijndael S-box},
	number = {US 10/816,791 -- 	EP 20030425211},
	year = {2004},
	month = {10/2004},
	type = {Grant},
	chapter = {US 7502464 B2 -- EP 1465365 A1 },
	abstract = {A method for implementing one-to-one binary functions defined on the Galois field GF(2^8) is very useful for forming fast and low power hardware devices regardless of the binary function. The method includes decoding an input byte for generating at least one bit string that contains only one active bit, and logically combining the bits of the bit string according to the binary function for generating a 256-bit string representing a corresponding output byte. The 256-bit string is then encoded in a byte for obtaining the output byte.},
	issn = {US 7502464 B2},
	author = {Macchetti, Marco and Fragneto, Pasqualina and Bertoni, Guido Marco}
}
@conference {26.BoFeDuPi2004,
	title = {A Methodology for Testing IPSec-based Systems},
	booktitle = {SoftCOM 2004},
	year = {2004},
	month = {October},
	pages = {22-26},
	address = {Split},
	abstract = {{IPSec is a suite of protocols adding security to communications at the IP level. This suite of protocols is becoming more and more important as it is included as mandatory security mechanism in IPv6. This paper focuses on a methodology for testing IPSec implementations. A UML model of the IPSec suite of protocols was developed. Test cases were obtained applying a coverage method on the same model.}},
	keywords = {encapsulating security payload (ESP), IPSec, security, testing, unified modeling language (UML)},
	author = {Boiko, Uljana and Ferrante, Alberto and Lo Duca, Antonietta and Piuri, Vincenzo}
}
@conference {23.BaLaPre2004,
	title = {UML in an Electronic System Level Design Methodology},
	booktitle = {UML-SOC{\textquoteright}04},
	year = {2004},
	month = {June 6},
	pages = {47-52},
	address = {San Diego, California},
	abstract = {The interest in System-On-Chip (SoC) design using the Unifed Modeling Language (UML) has been growing significantly during the last couple of years. In this paper we would like to present a methodology that aims to address embedded systems design issues at multiple levels of abstraction and to support a function/architecture codesign process. Our approach integrates UML with high-level synthesis and hardware/software co-verification techniques in order to provide an automated flow for SoC design starting from system-level specifications down to hardware/software partitioning and integration. UML has been selected because it is platform independent and helps team members to share very efficiently relevant information during the various design phases, while high-level synthesis helps to evaluate constraints that the embedded system must satisfy: e.g. performance, power and cost starting from behavioral specifications. The paper aims to give a contribution towards SoC Design automation from System-level specification to hardware/software partitioning.},
	keywords = {HW/SW co-design, methodology, system-on-chip (SoC), unified modeling language (UML)},
	author = {Basu, Ananda Shankar and Lajolo, Marcello and Prevostini, Mauro}
}
@conference {24.LaBaPre2004,
	title = {UML Specifications Towards a Codesign Environment},
	booktitle = {FDL{\textquoteright}04},
	year = {2004},
	month = {September 14-17},
	pages = {313-324},
	address = {Lille, France},
	abstract = {The Unified Modeling Language (UML) is receiving more and more attention from system designers that need to model both hardware and software related aspects of a system. On the ground of the growing consensus toward the need to raise the level of abstraction in system specifications, we would like to present a methodology that aims to address embedded systems design issues at multiple levels of abstraction and to support a function/architecture codesign process. Our approach integrates UML with high-level synthesis and hardware/software co-verification techniques in order to provide an automated flow for SoC design starting from system-level specifications down to hardware/software partitioning and integration. UML has been selected because it is platform independent and helps team member to share very efficiently relevant information during the various design phases, while high-level synthesis helps to evaluate constraints that the embedded system must satisfy: e.g. performance, power and cost starting from behavioral specifications.},
	keywords = {embedded systems, HW/SW co-design, system-on-chip (SoC), unified modeling language (UML)},
	author = {Lajolo, Marcello and Basu, Ananda Shankar and Prevostini, Mauro}
}
@inbook {19.1016432,
	title = {UML-based specifications of an embedded system oriented to HW/SW partitioning: a case study},
	booktitle = {Languages for system specification: Selected contributions on UML, systemC, system Verilog, mixed-signal systems, and property specification from FDL{\textquoteright}03},
	year = {2004},
	pages = {71-84},
	publisher = {Kluwer Academic Publishers},
	organization = {Kluwer Academic Publishers},
	address = {Norwell, MA, USA},
	abstract = {The Unified Modelling Language (UML) is a language for specifying, visualizing, constructing, and documenting the artefacts of software systems, as well as for modeling business and other non-software systems. The UML represents a collection of best engineering practices that succeeded in modelling large and complex systems; it is interesting to envision its extension for specification and modelling of hardware-software systems as well, starting with the first design phases, i.e. prior to hardware-software partitioning. This paper analyses the development of a solution able to define the hardware/software partitioning of an embedded system starting from its UML system specifications. The case study chosen is a Wireless Meter Reader (WMR) dedicated to the measurement of energy consumption. The designers evaluated the hardware/software partitioning solution in terms of cost, performance, size and consumption.},
	keywords = {embedded systems, HW/SW partitioning, system specifications, unified modeling language (UML)},
	isbn = {1-4020-7990-7},
	author = {Prevostini, Mauro and Balzarini, Francesco and Kostadinov, Atanas Nikolov and Mankan, Srinivas and Martinola, Aris and Minosi, Antonio}
}
@conference {11.BiMaBeBreZaFra2003,
	title = {About the Performances of the Advanced Encryption Standard in Embedded Systems with Cache Memory},
	booktitle = {ISCAS 2003},
	year = {2003},
	month = {May 25-28},
	pages = {145-148},
	address = {Bangkok},
	abstract = {Modern networked embedded systems represent a growing market segment in which security is becoming an essential requirement. The Advanced Encryption Standard (AES) specification is becoming the default choice for such type of systems; however, a proper software implementation of AES is of fundamental importance in order to achieve significant performance. Current implementations presented in literature differ in terms of the amount of look-up tables used for pre-computing the functions of the encryption/decryption phase. This raises some questions regarding which AES implementation is optimal for a specific system configuration that, up to now, have been only empirically solved. In this work, we present an analytical model to study and evaluate the performance of the possible AES implementations in the early phases of system development. We then show that the proposed high-level timing model captures, with significant accuracy, the actual performance of current AES applications and thus it can be used for early evaluation of optimal AES implementations and to support the design space exploration phase. Validating experiments have been carried out on the Lx architecture, a scalable and customizable VLIW architecture developed by STMicroelectronics and HP Labs. Some final considerations are eventually reported about the relevant characteristics of the analyzed implementations and the role of the cache memory.},
	doi = {http://dx.doi.org/10.1109/ISCAS.2003.1206212},
	author = {Bircan, Aril and Macchetti, Marco and Bertoni, Guido Marco and Breveglieri, Luca and Zaccaria, Vittorio and Fragneto, Pasqualina}
}
@conference {8.752733,
	title = {Efficient Software Implementation of AES on 32-Bit Platforms},
	booktitle = {CHES {\textquoteright}02: Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems},
	year = {2003},
	pages = {159{\textendash}171},
	publisher = {Springer-Verlag},
	organization = {Springer-Verlag},
	address = {London, UK},
	abstract = {Rijndael is the winner algorithm of the AES contest; therefore it should become the most used symmetric-key cryptographic algorithm. One important application of this new standard is cryptography on smart cards. In this paper we present an optimisation of the Rijndael algorithm to speed up execution on 32-bits processors with memory constraints, such as those used in smart cards. First a theoretical analysis of the Rijndael algorithm and of the proposed optimisation is discussed, and then simulation results of the optimised algorithm on different processors are presented and compared with other reference implementations, as known from the technical literature.},
	isbn = {3-540-00409-2},
	author = {Bertoni, Guido Marco and Breveglieri, Luca and Fragneto, Pasqualina and Macchetti, Marco and Marchesin, Stefano}
}
@article {13.MaBer2003,
	title = {Hardware Implementation of the Rijndael Sbox: a Case Study},
	journal = {ST Journal of System Research},
	year = {2003},
	month = {July},
	pages = {84-91},
	abstract = {The Rijndael algorithm was officially selected as the Advanced Encryption Standard in 2001 and will replace the DES in all applications, including Smart Card based products. For this kind of platform, a compact, area efficient hardware implementation of the algorithm is highly desirable. This paper describes such an implementation, which we have based on GF(28) finite field decomposition. We present our results from mappings on the STMicroelectronics ASIC technology library and discuss area, timing and power consumption figures.},
	author = {Macchetti, Marco and Bertoni, Guido Marco}
}
@conference {12.MiMaMaPreKoBa2003,
	title = {Intelligent, low-power and low-cost measurement system for energy consumption},
	booktitle = {VECIMS 2003},
	year = {2003},
	month = {July 27-29},
	pages = {125-130},
	address = {Lugano},
	abstract = {In the area of utility measurement systems, there is increasing awareness to the importance of using intelligent and secure meter readers. The aim is not simply that of reducing operational costs; aspects such as availability of real-time determination of consumption (mainly in the case of energy meters, but potentially also for water consumption etc.) are relevant not only for actions such as real-time billing but also in view of an increasing environmental awareness leading to {\textquoteright}preferential{\textquoteright} billing in particular times of the day or of the week and requiring availability of fine-grained statistics. All these actions in turn involve the requirement of data integrity; when utilities other than power providers are considered, the device should be battery-powered (and very long battery life must be granted), so that low-power design becomes a further requirement while being permanently either in active or in standby mode; moreover, not being connected to the power network means that wireless connections for transmitting and receiving information must be taken into account. Finally, these devices should be made available to the general public and thus be low-cost ones. This paper describes how all the above constraints have been analyzed in the design of a wireless meter reading system.},
	keywords = {measurement systems, meter reading systems, power consumption},
	author = {Minosi, Antonio and Martinola, Aris and Mankan, Srinivas and Prevostini, Mauro and Kostadinov, Atanas Nikolov and Balzarini, Francesco}
}
@Patent {10.pat20030068036PATENT,
	title = {Method and circuit for data encryption/decryption},
	number = {US 09/974,705},
	year = {2003},
	month = {April},
	type = {Grant},
	chapter = {US7801301 B2},
	abstract = {Data are converted between an unencrypted and an encrypted format according to the Rijndael algorithm, including a plurality of rounds. Each round is comprised of fixed set of transformations applied to a two-dimensional array, designated state, of rows and columns of bit words. At least a part of said transformations are applied on a transposed version of the state, wherein rows and columns are transposed for the columns and rows, respectively.},
	issn = {US7801301B2},
	author = {Macchetti, Marco and Marchesin, Stefano and Bondi, Umberto and Breveglieri, Luca and Bertoni, Guido Marco and Fragneto, Pasqualina}
}
@conference {14.MiMaMaBaKoPre2003,
	title = {UML-based Specifications of an Embedded System Oriented to HW/SW Partitioning: a Case Study},
	booktitle = {FDL{\textquoteright}03},
	year = {2003},
	month = {September 23-26},
	pages = {226-237},
	address = {Frankfurt},
	abstract = {The Unified Modelling Language (UML) is a language for specifying, visualizing, constructing, and documenting the artefacts of software systems, as well as for modelling business and other non-software systems. The UML represents a collection of best engineering practices that succeeded in modelling large and complex systems; it is interesting to envision its extension for specification and modelling of hardware-software systems as well, starting with the first design phases, i.e. prior to hardware-software partitioning. This paper analyses the development of a solution able to define the hardware/software partitioning of an embedded system starting from its UML system specifications. The case study chosen is a Wireless Meter Reader (WMR) dedicated to the measurement of energy consumption. The designers evaluated the hard-ware/software partitioning solution in terms of cost, performance, size and consumption.},
	keywords = {embedded systems, HW/SW partitioning, unified modeling language (UML)},
	author = {Minosi, Antonio and Mankan, Srinivas and Martinola, Aris and Balzarini, Francesco and Kostadinov, Atanas Nikolov and Prevostini, Mauro}
}
@conference {6.BoSaSciSiZaZa2002,
	title = {Energy Estimation and Optimization of Embedded VLIW Processors based on Instruction Clustering},
	booktitle = {39th Design Automation Conference},
	year = {2002},
	month = {June 10-14},
	pages = {886-891},
	address = {New Orleans},
	abstract = {Aim of this paper is to propose a methodology for the definition of an instruction-level energy estimation framework for VLIW (Very Long Instruction Word) processors. The power modeling methodology is the key issue to define an effective energy-aware software optimisation strategy for state-of-the-art ILP (Instruction Level Parallelism) processors. The methodology is based on an energy model for VLIW processors that exploits instruction clustering to achieve an efficient and fine grained energy estimation. The approach aims at reducing the complexity of the characterization problem for VLIW processors from exponential, with respect to the number of parallel operations in the same very long instruction, to quadratic, with respect to the number of instruction clusters. Furthermore, the paper proposes a spatial scheduling algorithm based on a low-power reordering of the parallel operations within the same long instruction. Experimental results have been carried out on the Lx processor, a 4-issue VLIW core jointly designed by HPLabs and STMicroelectronics. The results have shown an average error of 1:9\% between the cluster-based estimation model and the reference design, with a standard deviation of 5:8\%. For the Lx architecture, the spatial instruction scheduling algorithm provides an average energy saving of 12\%.},
	keywords = {power estimation, VLIW architectures},
	doi = {http://dx.doi.org/10.1109/DAC.2002.1012747},
	author = {Bona, Andrea and Sami, Mariagiovanna and Sciuto, Donatella and Silvano, Cristina and Zaccaria, Vittorio and Zafalon, Roberto}
}
@conference {4.BonaSaSciSiZaZa2002,
	title = {An Instruction-Level Methodology for Power Estimation and Optimization of Embedded VLIW cores},
	booktitle = {DATE 2002},
	year = {2002},
	month = {March 4-8},
	pages = {1128},
	address = {Paris},
	abstract = {The overall goal of this work is to define an instruction-level power macro-modeling and characterization methodology for VLIW embedded processor cores. The approach presented in this paper is a major extension of the work previously proposed in [1-3], targeting an instruction-level energy model to evaluate the energy consumption associated with a program execution on a pipelined VLIW core. Our first goal is the reduction of the complexity of the processor{\textquoteright}s energy model, without reducing the accuracy of the results. The second goal is to show how the energy model can be further simplified by introducing a methodology to automatically cluster the whole Instruction Set with respect to their average energy cost, in order to con verge to an highly effective design of experiments for the actual characterization task. The paper describes also the application of the proposed model to a real industrial VLIW core (the Lx Architecture developed by HP Labs and STMicroelectronics), to validate the effectiveness and accuracy of the proposed methodology.},
	doi = {http://dx.doi.org/10.1109/DATE.2002.998484},
	author = {Bona, Andrea and Sami, Mariagiovanna and Sciuto, Donatella and Silvano, Cristina and Zaccaria, Vittorio and Zafalon, Roberto}
}
@conference {1.371690,
	title = {Development cost and size estimation starting from high-level specifications},
	booktitle = {CODES {\textquoteright}01: Proceedings of the ninth international symposium on Hardware/software codesign},
	year = {2001},
	pages = {86-91},
	publisher = {ACM Press, New York, USA},
	organization = {ACM Press, New York, USA},
	address = {Copenhagen, Denmark},
	abstract = {This paper addresses the problem of estimating cost and development effort of a system, starting from its complete or partial high-level description. In addition, some modifications to evaluate the cost-effectiveness of reusing VHDL-based designs, are presented. The proposed approach has been formalized using an approach similar to the COCOMO analysis strategy, enhanced by a project size prediction methodology based on a VHDL function point metric. The proposed design size estimation methodology has been validated through a significant benchmark. The LEON-I microprocessor, whose VHDL description is of public domain.},
	keywords = {concurrent engineering, design reuse, process management, project size estimation, VHDL},
	isbn = {1-58113-364-2},
	doi = {http://dx.doi.org/10.1109/HSC.2001.924656},
	author = {Fornaciari, William and Salice, Fabio and Bondi, Umberto and Magini, Edi}
}
@conference {3.CaPoMaMaBeBreFra2001,
	title = {Efficient C implementation of the ECC and AES cryptographic systems},
	booktitle = {Technology Leadership Day - organized by the MicroSwiss Network},
	year = {2001},
	month = {October 10},
	address = {Fribourg},
	author = {Cassoli, Federico and Polloni, Flavio and Marchesin, Stefano and Macchetti, Marco and Bertoni, Guido Marco and Breveglieri, Luca and Fragneto, Pasqualina}
}
@conference {2.BoSaMa2001,
	title = {The {\textquoteright}Smart Card System{\textquoteright} project: From plastic money to mobile transaction support},
	booktitle = {Technology Leadership Day - organized by the MicroSwiss Network},
	year = {2001},
	month = {October 10},
	address = {Fribourg},
	author = {Bondi, Umberto and Saraceno, Giuseppe and Mazzoni, Luca}
}
