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Education and Innovation in Embedded Systems Design

USI Università della Svizzera italiana, USI Faculty of Informatics, Advanced Learning and Research Institute USI Università della Svizzera italiana USI Faculty of Informatics USI Advanced Learning and Research Institute
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E
Bellon, S., C. Favi, M. Malek, M. Macchetti, and F. Regazzoni, "Evaluating the Impact of Environmental Factors on Physically Unclonable Functions", International Symposium on Field-Programmable Gate Arrays FPGA 2016, Monterey, CA, USA, ACM New York, NY, USA, pp. 279, 02/2016.
Bu, L., C. Alippi, and D. Zhao, "Ensemble LSDD-based Change Detection Tests", IEEE-INNS International Joint Conference on Neural Networks (IJCNN16), Vancouver, Canada, 07/2016.
Baddour, R., A. Chiumento, and C. Desset, "Energy-Throughput Simulation Approach for Heterogeneous LTE scenarios", ISWCS'11: Proceedings of The Eighth International Symposium on Wireless Communication Systems, Aachen, Germany, pp. 1–5, November 6-9, 2011.
Bona, A., M. Sami, D. Sciuto, C. Silvano, V. Zaccaria, and R. Zafalon, "Energy Estimation and Optimization of Embedded VLIW Processors based on Instruction Clustering", 39th Design Automation Conference, New Orleans, pp. 886-891, June 10-14, 2002.
Sami, M., M. Malek, U. Bondi, and F. Regazzoni, "Embedded Systems Education: Job Market Expectations", Workshop on Embedded and Cyber-Physical Systems Education (WESE) , New Delhi, India, ACM, 10/2014.
Bertoni, G M., L. Breveglieri, P. Fragneto, M. Macchetti, and S. Marchesin, "Efficient Software Implementation of AES on 32-Bit Platforms", CHES '02: Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems, London, UK, Springer-Verlag, pp. 159–171, 2003.
Bertoni, G M., L. Breveglieri, P. Fragneto, M. Macchetti, and S. Marchesin, "Efficient Software Implementation of AES on 32-Bit Platforms", CHES '02: Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems, London, UK, Springer-Verlag, pp. 159–171, 2003.
Banik, S., A. Bogdanov, and F. Regazzoni, "Efficient Configurations for Block Ciphers with Unified ENC/DEC Paths", Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust (HOST) 2017, 2018.
Banik, S., A. Bogdanov, and F. Regazzoni, "Efficient Configurations for Block Ciphers with Unified ENC/DEC Paths", Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust (HOST) 2017, 2018.
Cassoli, F., F. Polloni, S. Marchesin, M. Macchetti, G M. Bertoni, L. Breveglieri, and P. Fragneto, "Efficient C implementation of the ECC and AES cryptographic systems", Technology Leadership Day - organized by the MicroSwiss Network, Fribourg, October 10, 2001.
Cassoli, F., F. Polloni, S. Marchesin, M. Macchetti, G M. Bertoni, L. Breveglieri, and P. Fragneto, "Efficient C implementation of the ECC and AES cryptographic systems", Technology Leadership Day - organized by the MicroSwiss Network, Fribourg, October 10, 2001.
Atasu, K., L. Breveglieri, and M. Macchetti, "Efficient AES implementations for ARM based platforms", SAC '04: Proceedings of the 2004 ACM symposium on Applied computing, Nicosia, Cyprus, ACM Press, New York, USA, pp. 841–845, 2004.
Bayrak, A. Galip, N. Velickovic, F. Regazzoni, D. Novo Bruna, P. Brisk, and P. Ienne, "An eda-friendly protection scheme against side-channel attacks", Design, Automation and Test in Europe (DATE), Grenoble, France, March, 2013.
Bayrak, A. Galip, N. Velickovic, F. Regazzoni, D. Novo Bruna, P. Brisk, and P. Ienne, "An eda-friendly protection scheme against side-channel attacks", Design, Automation and Test in Europe (DATE), Grenoble, France, March, 2013.
D
Mariani, G., R. Meeuws, G. Palermo, V-M. Sima, C. Silvano, and K. Bertels, "DRuiD: Designing Reconfigurable Architectures with Decision-making Support", 19th Asia and South Pacific Design Automation Conference (ASP-DAC), Singapore, 01/2014.
Fornaciari, W., F. Salice, U. Bondi, and E. Magini, "Development cost and size estimation starting from high-level specifications", CODES '01: Proceedings of the ninth international symposium on Hardware/software codesign, Copenhagen, Denmark, ACM Press, New York, USA, pp. 86-91, 2001.
Livi, L., F. Maria Bianchi, and C. Alippi, "Determination of the Edge of Criticality in Echo State Networks Through Fisher Information Maximization", IEEE Transactions on Neural Networks and Learning Systems, vol. 29, pp. 706-717, March, 2018.
Kavka, C., A. Turco, G. Palermo, C. Silvano, V. Zaccaria, G. Mariani, S. Bocchio, and F. Dongrui, "Design Space Exploration of Parallel Architectures", Multi-objective design space exploration of multiprocessor SoC architectures: the MULTICUBE approach, New York, USA, Springer, 2011.
Regazzoni, F., A. Cevrero, F-X. Standaert, S. Badel, T. Kluter, P. Brisk, Y. Leblebici, and P. Ienne, "A Design Flow and Evaluation Framework for DPA-resistant Instruction Set Extensions", Cryptographic Hardware and Embedded Systems (CHES), vol. 5747, Lausanne, Switzerland, Springer Berlin Heidelberg, pp. 205-219, September, 2009.
Regazzoni, F., A. Cevrero, F-X. Standaert, S. Badel, T. Kluter, P. Brisk, Y. Leblebici, and P. Ienne, "A Design Flow and Evaluation Framework for DPA-resistant Instruction Set Extensions", Cryptographic Hardware and Embedded Systems (CHES), vol. 5747, Lausanne, Switzerland, Springer Berlin Heidelberg, pp. 205-219, September, 2009.

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