ALaRI Hang Glider

Search form

Education and Innovation in Embedded Systems Design

USI Università della Svizzera italiana, USI Faculty of Informatics, Advanced Learning and Research Institute USI Università della Svizzera italiana USI Faculty of Informatics USI Advanced Learning and Research Institute
Search by content:
Search by:
Export 31 results:
Author Title [ Type(Desc)] Year
Filters: First Letter Of Last Name is H  [Clear All Filters]
Conference Paper
Dittrich, A., D. Solis Herrera, P. Coto, and M. Malek, "Responsiveness of Service Discovery in Wireless Mesh Networks", 20th Pacific Rim International Symposium on Dependable Computing (PRDC), Singapore, IEEE Computer Society, 11/2014.
Banik, S., A. Bogdanov, F. Regazzoni, T. Isobe, H. Hiwatari, and T. Akishita, "Round gating for low energy block ciphers", 2016 IEEE International Symposium on Hardware Oriented Security and Trust, HOST, McLean, VA, USA, IEEE Computer Society, pp. 55-60, 05/2016.
Baddour, R., A. Paspaliaris, and D. Solis Herrera, "SCV2: A model-based validation and verification approach to system-of-systems engineering", System of Systems Engineering Conference (SoSE), 2015 10th: IEEE, 05/2015.
O'Neill, M., E. O'Sullivan, G. McWilliams, M-J. Saarinen, C. Moore, A. Khalid, J. Howe, R. Del Pino, M. Abdalla, F. Regazzoni, et al., "Secure architectures of future emerging cryptography", International Conference on Computing Frontiers CF'16, Como, italy, ACM New York, pp. 315-322, 05/2016.
Howe, J., C. Moore, M. O'Neill, F. Regazzoni, T. Güneysu, and K.. Beeden, "Standard lattices in hardware", Proceedings of the 53rd Annual Design Automation Conference DAC 2016, Austin, TX, USA, ACM, pp. 162, 06/2016.
Journal Article
Barenghi, A., C. Hocquet, D. Bol, F-X. Standaert, F. Regazzoni, and I. Koren, "A Combined Design-Time/Test-Time Study of the Vulnerability of Sub-Threshold Devices to Low Voltage Fault Attacks", IEEE Transactions on Emerging Topics in Computing, vol. PP, issue 99, 04/2014.
Bol, D., C. Hocquet, and F. Regazzoni, "A Fast ULV Logic Synthesis Flow in Many-Vt CMOS Processes for Minimum Energy Under Timing Constraints", IEEE Transactions on Circuits and Systems II: Express Briefs , vol. 59-II, issue 12, pp. 947-951, 02/2012.
Bol, D., C. Hocquet, and F. Regazzoni, "A Fast ULV Logic Synthesis Flow in Many-Vt CMOS Processes for Minimum Energy under Timing Constraints", IEEE Transactions on Circuits and Systems II, vol. 59, issue 12, pp. 947-951, 2013.
Hocquet, C., D. Kamel, F. Regazzoni, J-D. Legat, D. Flandre, D. Bol, and F-X. Standaert, "Harvesting the potential of nano-CMOS for lightweight cryptography: An ultra-low-voltage 65 nm AES coprocessor for passive RFID tags", Springer Journal of Cryptographic Engineering, vol. 1, issue 1, 2011.
Regazzoni, F., S. Banik, A. Bogdanov, T. Isobe, K. Shibutani, H. Hiwatari, and T. Akishita, "Midori: (A) Block Cipher for Low Energy (Extended Version)", (IACR) Cryptology ePrint Archive, vol. 2015, 12/2015.
Howe, J., A. Khalid, C. Rafferty, F. Regazzoni, and M. O'Neill, "On Practical Discrete Gaussian Samplers For Lattice-Based Cryptography", IEEE Transaction on Computers, In Press.

Pages