Export 106 results:
Author Title Type [ Year] Filters: First Letter Of Last Name is F [Clear All Filters]
"Development cost and size estimation starting from high-level specifications",
CODES '01: Proceedings of the ninth international symposium on Hardware/software codesign, Copenhagen, Denmark, ACM Press, New York, USA, pp. 86-91, 2001.
"Efficient C implementation of the ECC and AES cryptographic systems",
Technology Leadership Day - organized by the MicroSwiss Network, Fribourg, October 10, 2001.
"About the Performances of the Advanced Encryption Standard in Embedded Systems with Cache Memory",
ISCAS 2003, Bangkok, pp. 145-148, May 25-28, 2003.
"Efficient Software Implementation of AES on 32-Bit Platforms",
CHES '02: Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems, London, UK, Springer-Verlag, pp. 159–171, 2003.
Method and circuit for data encryption/decryption,
, no. US 09/974,705, April, 2003.
Method of implementing one-to-one binary function and relative hardware device, especially for a Rijndael S-box,
, no. US 10/816,791 -- EP 20030425211, 10/2004.
"A Methodology for Testing IPSec-based Systems",
SoftCOM 2004, Split, pp. 22-26, October, 2004.
"Application-Driven Optimization of VLIW Architectures: A Hardware-Software Approach",
RTAS '05: Proceedings of the 11th IEEE Real Time on Embedded Technology and Applications Symposium, Washington, DC, USA, IEEE Computer Society, pp. 128–137, 03/2005.
"Scheduling Small Packets in IPSec-based Systems",
CCNC, Las Vegas, NV, USA, January 8, 2006.
"Speeding Up AES By Extending a 32 bit Processor Instruction Set",
ASAP '06: Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06), Washington, DC, USA, IEEE Computer Society, pp. 275-282, 2006.
"A Data protection Unit for NoC-based Architecture",
CODES+ISSS 2007, in proceedings of the Fifth IEEE/ACM/FIP International Conference of Hardware/Software Codesign and System Synthesis (CODES+ISSS 2007), Salzburg, Austria, September 30, 2007.
"Design exploration for an Ogg/Vorbis decoder for VLIW architectures",
Workshop on Application Specific Processors (WASP '07), Salzburg, Austria, October, 2007.
"High-level Architecture of an IPSec-dedicated System on Chip",
proceedings of NGI 2007, Trondheim, Norway, IEEE Press, May, 2007.
"A Memory Unit for Priority Management in IPSec Accelerators",
proceedings of ICC07. Glasgow, Scotland: IEEE Communications Society, Glasgow, Scotland, June 24, 2007.
"Power Modeling and Power Analysis for IEEE 802.15.4: a Concurrent State Machine Approach",
Proceedings of CCNC 2007, Las Vegas, USA, January 11-13, 2007.
"A Query Unit for the IPSec Databases",
SECRYPT 2007, Barcelona, Spain, 07/2007.
"Scheduling Small packets in IPSec Multi-accelerator Based Systems",
Journal of Communication(JCM) Academy publisher, vol. 2, no. 2, Stresa, Italy, pp. 53-60, March, 2007.
"Security Aspects in Networks-on-Chips: Overview and Proposals for Secure Implementations",
DSD07, in proceedings of 10th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD 07), Lübeck, Germany, August 29-31, 2007.
"Self-adaptive Security at Application Level: a Proposal",
ReCoSoC 2007, Jun. 2007, in proceedings of ReCoSoC 2007, June, 2007.
"Self-adaptive Security at Application Level: a Proposal",
ReCoSoC 2007, Jun. 2007, in proceedings of ReCoSoC 2007, June, 2007.