Export 13 results:
Author Title [ Type] Year Filters: First Letter Of Last Name is I and Author is Paolo Ienne [Clear All Filters]
"Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology",
Springer Transactions on Computational Science, vol. 5430, pp. 230–243, February, 2009.
"Automatic Application of Power Analysis Countermeasures",
IEEE Transactions on Computers, vol. PP, issue 99, 12/2013.
"Automatic Application of Power Analysis Countermeasures",
IEEE Transactions on Computers , vol. 64, issue 2, pp. 329-341, 02/2015.
"Sleuth: Automated Verification of Software Power Analysis Countermeasures",
Workshop on Cryptographic Hardware and Embedded Systems (CHES), Santa Barbara, California, USA, August, 2013.
"Simulation-based Methodology for Evaluating DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies",
International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS IC 07), Samos, Greece, July 16-19, 2007.
"Power-Gated MOS Current Mode Logic (PG-MCML): A Power-Aware DPA-Resistant Standard Cell Library",
48th Design Automation Conference (DAC), San Diego, Califorina, June, 2011.
"Power Attacks Resistance of Cryptographic S-boxes with added Error Detection Circuits",
proceedings of: '22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'07), Rome, Italy, September 26-28, 2007.
"Instruction Set Extensions for secure applications",
Design, Automation Test in Europe Conference DATE 2016, Dresden, Germany, IEEE, pp. 1529-1534, 03/2016.
"A First Step Towards Automatic Application of Power Analysis Countermeasures",
48th Design Automation Conference (DAC), San Diego, Califorina, June, 2011.
"An eda-friendly protection scheme against side-channel attacks",
Design, Automation and Test in Europe (DATE), Grenoble, France, March, 2013.
"Can knowledge regarding the presence of countermeasures against fault attacks simplify power attacks on cryptographic devices?",
Proceedings of 23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS 08), October 1-3, 2008.
"Interaction between Fault Attack Countermeasures and the Resistance against Power Analysis Attacks",
Fault Analysis in Cryptography: Springer Berlin Heidelberg, pp. 257-272, 2012.
"A Design Flow and Evaluation Framework for DPA-resistant Instruction Set Extensions",
Cryptographic Hardware and Embedded Systems (CHES), vol. 5747, Lausanne, Switzerland, Springer Berlin Heidelberg, pp. 205-219, September, 2009.