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Education and Innovation in Embedded Systems Design

USI Università della Svizzera italiana, USI Faculty of Informatics, Advanced Learning and Research Institute USI Università della Svizzera italiana USI Faculty of Informatics USI Advanced Learning and Research Institute
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Patent
Macchetti, M., P. Fragneto, and G M. Bertoni, Method of implementing one-to-one binary function and relative hardware device, especially for a Rijndael S-box, , no. US 10/816,791 -- EP 20030425211, 10/2004.
Macchetti, M., S. Marchesin, U. Bondi, L. Breveglieri, G M. Bertoni, and P. Fragneto, Method and circuit for data encryption/decryption, , no. US 09/974,705, April, 2003.
Macchetti, M., S. Marchesin, U. Bondi, L. Breveglieri, G M. Bertoni, and P. Fragneto, Method and circuit for data encryption/decryption, , no. US 09/974,705, April, 2003.
Macchetti, M., S. Marchesin, U. Bondi, L. Breveglieri, G M. Bertoni, and P. Fragneto, Method and circuit for data encryption/decryption, , no. US 09/974,705, April, 2003.
Journal Article
Banik, S., V. Mikhalev, F. Armknecht, T. Isobe, W. Meier, A. Bogdanov, Y. Watanabe, and F. Regazzoni, "Towards Low Energy Stream Ciphers", IACR Transactions on Symmetric Cryptology, In Press.
Banik, S., V. Mikhalev, F. Armknecht, T. Isobe, W. Meier, A. Bogdanov, Y. Watanabe, and F. Regazzoni, "Towards Low Energy Stream Ciphers", IACR Transactions on Symmetric Cryptology, In Press.
Becker, G., F. Regazzoni, C. Paar, and W. Burleson, "Stealthy Dopant-Level Hardware Trojans: Extended Version", Journal of Cryptographic Engineering, vol. 4, issue 1, pp. 19-31, 04/2014.
Becker, G., F. Regazzoni, C. Paar, and W. Burleson, "Stealthy Dopant-Level Hardware Trojans: Extended Version", Journal of Cryptographic Engineering, vol. 4, issue 1, pp. 19-31, 04/2014.
Barenghi, A., G. Pelosi, and F. Regazzoni, "Simulation-Time Security Margin Assessment against Power-Based Side Channel Attacks", (IACR) Cryptology ePrint Archive, vol. 2014, 05/2014.
Bo, L., C. Alippi, and D. Zhao, "A Pdf-free Change Detection Test Based on Density Difference Estimation", IEEE Transactions on Neural Networks and Learning Systems, vol. 29, issue 2, pp. 324 - 334, 11/2016, 2018.
Bianchi, F. Maria, L. Livi, C. Alippi, and R. Jenssen, "Multiplex visibility graphs to investigate recurrent neural network dynamics", Nature-Scientific reports, vol. 7, pp. 44037-44049, 03/2017.
Regazzoni, F., S. Banik, A. Bogdanov, T. Isobe, K. Shibutani, H. Hiwatari, and T. Akishita, "Midori: (A) Block Cipher for Low Energy (Extended Version)", (IACR) Cryptology ePrint Archive, vol. 2015, 12/2015.
Regazzoni, F., S. Banik, A. Bogdanov, T. Isobe, K. Shibutani, H. Hiwatari, and T. Akishita, "Midori: (A) Block Cipher for Low Energy (Extended Version)", (IACR) Cryptology ePrint Archive, vol. 2015, 12/2015.
Zhao, D., L. Bu, C. Alippi, and Q. Wei, "A Kolmogorov-Smirnov Test to Detect Changes in Stationarity in Big Data", IFAC-PapersOnLine, vol. 50, pp. 14260 - 14265, 2017.
Brannigan, S., N. Smyth, T. Oder, F. Valencia, E. O'Sullivan, T. Güneysu, and F. Regazzoni, "An Investigation of Sources of Randomness Within Discrete Gaussian Sampling", IACR Cryptology ePrint Archive, vol. 2017, pp. 298, 2017.
Bianchi, F. Maria, L. Livi, and C. Alippi, "Investigating echo state networks dynamics by means of recurrence analysis", IEEE Transactions on Neural Networks and Learning Systems, vol. 29, pp. 427 - 439, 02/2018.
Bu, L., D. Zhao, and C. Alippi, "An Incremental Change Detection Test Based on Density Difference Estimation", IEEE Transactions on Systems, Man, and Cybernetics: Systems, vol. 47, pp. 2714-2726, Oct, 2017.
Hocquet, C., D. Kamel, F. Regazzoni, J-D. Legat, D. Flandre, D. Bol, and F-X. Standaert, "Harvesting the potential of nano-CMOS for lightweight cryptography: An ultra-low-voltage 65 nm AES coprocessor for passive RFID tags", Springer Journal of Cryptographic Engineering, vol. 1, issue 1, 2011.
Macchetti, M., and G M. Bertoni, "Hardware Implementation of the Rijndael Sbox: a Case Study", ST Journal of System Research, pp. 84-91, July, 2003.
Bol, D., C. Hocquet, and F. Regazzoni, "A Fast ULV Logic Synthesis Flow in Many-Vt CMOS Processes for Minimum Energy under Timing Constraints", IEEE Transactions on Circuits and Systems II, vol. 59, issue 12, pp. 947-951, 2013.

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