Upasani, G., A. Calimera, A. Macii, E. Macii, and M. Poncino, "Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering", Proceedings of the 19th international workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2009), Delft, The Netherlands, September 9-11, 2009.

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