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Education and Innovation in Embedded Systems Design

USI Università della Svizzera italiana, USI Faculty of Informatics, Advanced Learning and Research Institute USI Università della Svizzera italiana USI Faculty of Informatics USI Advanced Learning and Research Institute
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Journal Article
Barenghi, A., C. Hocquet, D. Bol, F-X. Standaert, F. Regazzoni, and I. Koren, "A Combined Design-Time/Test-Time Study of the Vulnerability of Sub-Threshold Devices to Low Voltage Fault Attacks", IEEE Transactions on Emerging Topics in Computing, vol. PP, issue 99, 04/2014.
Banik, S., A. Bogdanov, and F. Regazzoni, "Compact Circuits for Combined AES", Journal of Cryptographic Engineering, In Press.
Roy, D. Basu, M. Alam, S. Bhattacharya, V. Govindan, F. Regazzoni, R. Subhra Chakraborty, and D. Mukhopadhyay, "Customized Instructions for Protection Against Memory Integrity Attacks", IEEE Embedded Systems Letters, In Press.
Roy, D. Basu, M. Alam, S. Bhattacharya, V. Govindan, F. Regazzoni, R. Subhra Chakraborty, and D. Mukhopadhyay, "Customized Instructions for Protection Against Memory Integrity Attacks", IEEE Embedded Systems Letters, In Press.
Regazzoni, F., T. Eisenbarth, A. Poschmann, J. Groschdl, F. Gurkaynak, M. Macchetti, Z. Toprak, L. Pozzi, C. Paar, Y. Leblebici, et al., "Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology", Springer Transactions on Computational Science, vol. 5430, pp. 230–243, February, 2009.
Banik, S., A. Bogdanov, and F. Regazzoni, "Exploring Energy Efficiency of Lightweight Block Ciphers", (IACR) Cryptology ePrint Archive, vol. 2015, 09/2015.
Bol, D., C. Hocquet, and F. Regazzoni, "A Fast ULV Logic Synthesis Flow in Many-Vt CMOS Processes for Minimum Energy Under Timing Constraints", IEEE Transactions on Circuits and Systems II: Express Briefs , vol. 59-II, issue 12, pp. 947-951, 02/2012.
Bol, D., C. Hocquet, and F. Regazzoni, "A Fast ULV Logic Synthesis Flow in Many-Vt CMOS Processes for Minimum Energy under Timing Constraints", IEEE Transactions on Circuits and Systems II, vol. 59, issue 12, pp. 947-951, 2013.
Hocquet, C., D. Kamel, F. Regazzoni, J-D. Legat, D. Flandre, D. Bol, and F-X. Standaert, "Harvesting the potential of nano-CMOS for lightweight cryptography: An ultra-low-voltage 65 nm AES coprocessor for passive RFID tags", Springer Journal of Cryptographic Engineering, vol. 1, issue 1, 2011.
Brannigan, S., N. Smyth, T. Oder, F. Valencia, E. O'Sullivan, T. Güneysu, and F. Regazzoni, "An Investigation of Sources of Randomness Within Discrete Gaussian Sampling", IACR Cryptology ePrint Archive, vol. 2017, pp. 298, 2017.
Regazzoni, F., S. Banik, A. Bogdanov, T. Isobe, K. Shibutani, H. Hiwatari, and T. Akishita, "Midori: (A) Block Cipher for Low Energy (Extended Version)", (IACR) Cryptology ePrint Archive, vol. 2015, 12/2015.
Alippi, C., S. Ntalampiras, and M. Roveri, "Model-Free Fault Detection and Isolation in Large-Scale Cyber-Physical Systems", IEEE Transactions on Emerging Topics in Computational Intelligence, vol. 1, pp. 61-71, Feb, 2017.
Alippi, C., and M. Roveri, "The (Not) Far-Away Path to Smart Cyber-Physical Systems: An Information-Centric Framework", Computer, vol. 50, pp. 38-47, April, 2017.
Howe, J., A. Khalid, C. Rafferty, F. Regazzoni, and M. O'Neill, "On Practical Discrete Gaussian Samplers For Lattice-Based Cryptography", IEEE Transaction on Computers, In Press.
Howe, J., A. Khalid, C. Rafferty, F. Regazzoni, and M. O'Neill, "On Practical Discrete Gaussian Samplers For Lattice-Based Cryptography", IEEE Transaction on Computers, In Press.
Pilato, C., S. Garg, R. Karri, and F. Regazzoni, "Securing Hardware Accelerators: a New Challenge for High-Level Synthesis", IEEE Embedded Systems Letters, vol. 3, issue 10, pp. 77-80, 11/2017, 2018.
Barenghi, A., G. Pelosi, and F. Regazzoni, "Simulation-Time Security Margin Assessment against Power-Based Side Channel Attacks", (IACR) Cryptology ePrint Archive, vol. 2014, 05/2014.
Becker, G., F. Regazzoni, C. Paar, and W. Burleson, "Stealthy Dopant-Level Hardware Trojans: Extended Version", Journal of Cryptographic Engineering, vol. 4, issue 1, pp. 19-31, 04/2014.
Derin, O., E. Cannella, G. Tuveri, P. Meloni, T. Stefanov, L. Fiorin, L. Raffo, and M. Sami, "A system-level approach to adaptivity and fault-tolerance in NoC-based MPSoCs: The MADNESS project.", Microprocessors and Microsystems - Embedded Hardware Design, vol. 37, issue 6-7, pp. 515–529, 2013.
Pilato, C., S. Garg, K. Wu, R. Karri, and F. Regazzoni, "TaintHLS: High-Level Synthesis For Dynamic Information Flow Tracking", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, In Press.

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