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Education and Innovation in Embedded Systems Design

USI Università della Svizzera italiana, USI Faculty of Informatics, Advanced Learning and Research Institute USI Università della Svizzera italiana USI Faculty of Informatics USI Advanced Learning and Research Institute
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C
Widmann, D., K. Balać, A V. Taddeo, M. Prevostini, and A. Puiatti, "Characterization of In-tunnel Distance Measurements for Vehicle Localization", IEEE Wireless Communications and Networking Conference (WCNC), Shanghai, P.R. China, 2013.
Widmann, D., K. Balać, A V. Taddeo, M. Prevostini, and A. Puiatti, "Characterization of In-tunnel Distance Measurements for Vehicle Localization", IEEE Wireless Communications and Networking Conference (WCNC), Shanghai, P.R. China, 2013.
Regazzoni, F., R. Graves, G. Di Natale, L. Batina, S. Bhasin, B. Ege, A. P. Fournaris, N. Mentens, S. Picek, V. Rozic, et al., "Challenges in designing trustworthy cryptographic co-processors", IEEE International Symposium on Circuits and Systems (ISCAS) 2015, Lisbon, Portugal, IEEE, pp. 2009-2012, 09/2015.
Bailey, D. V., B. Baldwin, L. Batina, D. J. Bernstein, P. Birkner, J. W. Bos, G. van Damme, G. de Meulenaer, J. Fan, F. Gurkaynak, et al., "The Certicom Challenges ECC2-X", Workshop on Special Purpose Hardware for Attacking Cryptographic Systems (SHARCS), Lausanne, Switzerland, September, 2009.
Ciobanu, C. B., G. Gaydadjiev, C. Pilato, and D. Sciuto, "The Case for Polymorphic Registers in Dataflow Computing", International Journal of Parallel Programming, vol. 54, issue 5, pp. 54-62, 10/2018.
Prevostini, M., A V. Taddeo, K. Balać, M. Jermini, and C. Linder, "Calibration and in-Field Validation Tests of a Web-based Adaptive Management System for Monitoring - Scaphoideus titanus", Future Integrated Pest Management in Europe, 2013.
B
Sivakumar, G., and M. Prevostini, "Bridging the Gap between SysML and Design Space Exploration", FDL'06 Proceedings, Darmstadt, Germany, pp. 389-394, September 19-22, 2006.
Pilato, C., "Bridging the Gap between Software and Hardware Designers Using High-Level Synthesis", Advances in Parallel Computing, 2018.
Bailey, D. V., L. Batina, D. J. Bernstein, P. Birkner, J. W. Bos, H. - Chung Chen, C. - Mou Cheng, G. van Damme, T. Güneysu, F. Gurkaynak, et al., "Breaking ECC2K-130", IACR Cryptology ePrint Archive, vol. 2009, pp. 541, 11/2009.
Pilato, C., K. Basu, F. Regazzoni, and R. Karri, "Black-Hat High-Level Synthesis: Myth or Reality?", IEEE Transactions on Very Large Scale Integration Systems, In Press.
Krdu, A., Y. Lebrun, U. Ahmad, S. Pollin, and M. Li, "Beamforming for interference mitigation and its implementation on an SDR baseband processor", SiPS'11: Proceedings of the IEEE Workshop on Signal Processing Systems, Beirut, Lebanon, pp. 1–6, October 4-7, 2011.
A
Mariani, G., G. Palermo, C. Silvano, and V. Zaccaria, "ARTE: an Application-specific Run-Time Management Framework for Multi-core Systems", Proceedings IEEE SASP'11 - Symposium on Application Specific Processors, San Diego, CA, USA, June, 2011.
Mariani, G., G. Palermo, V. Zaccaria, and C. Silvano, "ARTE: an Application-specific Run-Time Management Framework for Multi-cores based on Queuing Models", Parallel Computing, 2013.
Palermo, G., G. Mariani, C. Silvano, R. Locatelli, and M. Coppola, "Application-Specific Topology Design Customization for STNoC", DSD07, in proceedings of 10th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD 07), Lübeck, Germany, August 29-31, 2007.
Ferrante, A., G. Piscopo, and S. Scaldaferri, "Application-Driven Optimization of VLIW Architectures: A Hardware-Software Approach", RTAS '05: Proceedings of the 11th IEEE Real Time on Embedded Technology and Applications Symposium, Washington, DC, USA, IEEE Computer Society, pp. 128–137, 03/2005.
Gamrat, C., J-M. Philippe, C. Jesshope, A. Shafarenko, L. Bisdounis, U. Bondi, A. Ferrante, J. Cabestany, M. Huebner, J. Parsinnen, et al., "AETHER: Self-Adaptive Networked Entities: Autonomous Computing Elements for Future Pervasive Applications and Technologies", Reconfigurable Computing: From FPGAs to Hardware/Software Codesign, New York, USA, Springer, pp. 149–184, 2011.
Gamrat, C., J-M. Philippe, C. Jesshope, A. Shafarenko, L. Bisdounis, U. Bondi, A. Ferrante, J. Cabestany, M. Huebner, J. Parsinnen, et al., "AETHER: Self-Adaptive Networked Entities: Autonomous Computing Elements for Future Pervasive Applications and Technologies", Reconfigurable Computing: From FPGAs to Hardware/Software Codesign, New York, USA, Springer, pp. 149–184, 2011.
Cappiello, C., A. Hinostroza, B. Pernici, M. Sami, E. Henis, R. I. Kat, K. Z. Meth, and M. Mura, "ADSC: Application-Driven Storage Control for Energy Efficiency", Information and Communication on Technology for the Fight against Global Warming - First International Conference ICT-GLOW, vol. 6868, Toulouse, France, Springer, pp. 165-179, 08/2011.
Bonesana, I., M. Paolieri, and M D. Santambrogio, "An adaptable FPGA-based System for Regular Expression Matching", Proceedings of Design, Automation and Test in Europe (DATE) Conference, Munich, Germany, March 10-14, 2008.
Banik, S., A. Bogdanov, T. Fanni, C. Sau, L. Raffo, F. Palumbo, and F. Regazzoni, "Adaptable AES implementation with power-gating support", International Conference on Computing Frontiers CF'16, Como, Italy, ACM Ney York, NY, USA, pp. 331-334, 05/2016.

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