Export 204 results:
Author [ Title
] Type Year Filters: First Letter Of Last Name is M [Clear All Filters]
"Optimization Algorithms for Embedded System Design Space Exploration",
Multi-objective design space exploration of multiprocessor SoC architectures: the MULTICUBE approach, New York, USA, Springer, 2011.
"Optimizing Failure Prediction to Maximize Availability",
13th IEEE International Conference on Autonomic Computing (ICAC), Würzburg, Germany, 07/2016.
"Optimizing Sensor Nodes Placement for Fault-tolerant Trilateration-based Localization",
IEEE Pacific Rim International Symposium on Dependable Computing (PRDC), Zhangjiajie, China, 11/2015.
"OSCAR: an Optimization Methodology Exploiting Spatial Correlation in Multi-core Design Space",
IEEE Transactions on Computer-Aided Design, vol. 21, issue 5, no. -: IEEE, pp. 740-753, 05/2012.
"Power and Performance Optimized Hardware Classifiers for Eefficient On-device Malware Detection",
Cryptography and Security in Computing Systems, Valencia, Spain, ACM, 01/2019.
"Power Modeling and Power Analysis for IEEE 802.15.4: a Concurrent State Machine Approach",
Proceedings of CCNC 2007, Las Vegas, USA, January 11-13, 2007.
"Predictive Analytics: A Shortcut to Dependable Computing",
Software Engineering for Resilient Systems, Cham, Springer International Publishing, 2017.
"Proactive Failure Management in Smart Grids for Improved Resilience (A Methodology for Failure Prediction and Mitigation)",
IEEE GLOBECOM SmartGrid Resilience (SGR) Workshop, San Diego, CA, USA, 12/2015.
"Progettazione e valutazione di soluzioni wireless multi-hop per il monitoraggio ambientale",
MIARIA: Techologia e Conoscenza al Servizio della Sicurezza, Missaglia, Italy, Bellavite, pp. 108-120, 2011.
"Progettazione e valutazione di soluzioni wireless multi-hop per il monitoraggio ambientale",
MIARIA: Techologia e Conoscenza al Servizio della Sicurezza, Missaglia, Italy, Bellavite, pp. 108-120, 2011.
"QoS and Security in Energy-harvesting Wireless Sensor Networks",
Proceedings of ICETE SECRYPT, Athens, Greece, July, 2010.
"Quasi-Pipelined Hash Circuits",
IEEE ARITH 17, Cape Cod, pp. 222-229, June, 2005.
Reconfigurable Logic Circuit,
, no. GB1719355.8, 11/2017, Submitted.
"Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering",
Proceedings of the 19th international workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2009), Delft, The Netherlands, September 9-11, 2009.
"Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering",
Proceedings of the 19th international workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2009), Delft, The Netherlands, September 9-11, 2009.
"A Resource-optimized Approach to Efficient Early Detection of Mobile Malware",
3rd International Workshop on Security of Mobile Applications - IWSMA 2014, Fribourg, Switzerland, 09/2014.
"A Resource-optimized Approach to Efficient Early Detection of Mobile Malware",
3rd International Workshop on Security of Mobile Applications - IWSMA 2014, Fribourg, Switzerland, 09/2014.
"Response Surface Modeling for Embedded System Design Space Exploration",
Multi-objective design space exploration of multiprocessor SoC architectures: the MULTICUBE approach, New York, USA, Springer, 2011.
"Responsiveness of Service Discovery in Wireless Mesh Networks",
20th Pacific Rim International Symposium on Dependable Computing (PRDC), Singapore, IEEE Computer Society, 11/2014.
"Rethinking Secure FPGAs: TowardsCryptography-friendly Configurable Cell Architecture and its Automated Design Flow",
Proceedings of FCCM, 05/2018.