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Education and Innovation in Embedded Systems Design

USI Università della Svizzera italiana, USI Faculty of Informatics, Advanced Learning and Research Institute USI Università della Svizzera italiana USI Faculty of Informatics USI Advanced Learning and Research Institute
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2008
Luković, S., and L. Fiorin, "An Automated Design Flow for NoC-based MPSoCs on FPGA", RSP 2008, The 19th IEEE/IFIP International Symposium on Rapid System Prototyping, Monterey, USA/CA, June 2-5, 2008.
Fiorin, L., S. Luković, and G. Palermo, "Implementation of a Reconfigurable Data Protection Module for NoC-based MPSoCs", Proceedings of the 21st IPDPS 2007 Reconfigurable Architecture Workshop (RAW), 21th IEEE International Parallel and Distributed Processing Symposium, Miami, USA/FL, April, 2008.
Mura, M., F. Fabbri, and M. Sami, "Modelling the Power Cost of Security in Wireless Sensor Networks : the Case of 802.15.4", Proceedings of IEEE ICT08, Saint Petersburg, Russia, June, 2008.
Ferrante, A., R. Pompei, A. Stulova, and A V. Taddeo, "A Protocol For Pervasive Distributed Computing Reliability", SecPri_WiMob 2008, Avignon, France, IEEE, 10/2008.
Fiorin, L., G. Palermo, S. Luković, V. Catalano, and C. Silvano, "Secure Memory Accesses on Networks-on-Chip", IEEE Transactions on Computers, vol. 57, no. 9, pp. 1216-1229, September, 2008.
Fiorin, L., G. Palermo, and C. Silvano, "A Security Monitoring Service for NoCs", Sixth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'08), Atlanta, Georgia, USA., 10/2008.
2007
Fiorin, L., G. Palermo, S. Luković, and C. Silvano, "A Data protection Unit for NoC-based Architecture", CODES+ISSS 2007, in proceedings of the Fifth IEEE/ACM/FIP International Conference of Hardware/Software Codesign and System Synthesis (CODES+ISSS 2007), Salzburg, Austria, September 30, 2007.
Ferrari, F., and E. Amador, "Design exploration for an Ogg/Vorbis decoder for VLIW architectures", Workshop on Application Specific Processors (WASP '07), Salzburg, Austria, October, 2007.
Ferrante, A., and V. Piuri, "High-level Architecture of an IPSec-dedicated System on Chip", proceedings of NGI 2007, Trondheim, Norway, IEEE Press, May, 2007.
Dadda, L., A. Ferrante, and M. Macchetti, "A Memory Unit for Priority Management in IPSec Accelerators", proceedings of ICC07. Glasgow, Scotland: IEEE Communications Society, Glasgow, Scotland, June 24, 2007.
Mura, M., M. Paolieri, L. Negri, F. Fabbri, and M. Sami, "Power Modeling and Power Analysis for IEEE 802.15.4: a Concurrent State Machine Approach", Proceedings of CCNC 2007, Las Vegas, USA, January 11-13, 2007.
Ferrante, A., S. Chandra, and V. Piuri, "A Query Unit for the IPSec Databases", SECRYPT 2007, Barcelona, Spain, 07/2007.
Taddeo, A V., and A. Ferrante, "Scheduling Small packets in IPSec Multi-accelerator Based Systems", Journal of Communication(JCM) Academy publisher, vol. 2, no. 2, Stresa, Italy, pp. 53-60, March, 2007.
Fiorin, L., C. Silvano, and M. Sami, "Security Aspects in Networks-on-Chips: Overview and Proposals for Secure Implementations", DSD07, in proceedings of 10th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD 07), Lübeck, Germany, August 29-31, 2007.
Ferrante, A., A V. Taddeo, M. Sami, F. Mantovani, and J. Fridkins, "Self-adaptive Security at Application Level: a Proposal", ReCoSoC 2007, Jun. 2007, in proceedings of ReCoSoC 2007, June, 2007.
Ferrante, A., A V. Taddeo, M. Sami, F. Mantovani, and J. Fridkins, "Self-adaptive Security at Application Level: a Proposal", ReCoSoC 2007, Jun. 2007, in proceedings of ReCoSoC 2007, June, 2007.
2006
Taddeo, A V., A. Ferrante, and V. Piuri, "Scheduling Small Packets in IPSec-based Systems", CCNC, Las Vegas, NV, USA, January 8, 2006.
Bertoni, G M., L. Breveglieri, R. Farina, and F. Regazzoni, "Speeding Up AES By Extending a 32 bit Processor Instruction Set", ASAP '06: Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06), Washington, DC, USA, IEEE Computer Society, pp. 275-282, 2006.
2005
Ferrante, A., G. Piscopo, and S. Scaldaferri, "Application-Driven Optimization of VLIW Architectures: A Hardware-Software Approach", RTAS '05: Proceedings of the 11th IEEE Real Time on Embedded Technology and Applications Symposium, Washington, DC, USA, IEEE Computer Society, pp. 128–137, 03/2005.

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