]
"ReCPU: a Parallel and Pipelined Architecture for Regular Expression Matching",
Proceedings of 15th Annual IFIP International Conference on Very Large Scale Integration {(IFIP-VLSI 07)},(best paper award), Atlanta, Georgia, USA, October 15-17, 2007.
"Mapping and Topology Customization Approaches for Application-Specific STNoC Designs",
IEEE Proceedings of ASAP'07 - 18th International Conference on Application-specific Systems, Architectures and Processors, Montréal, Québec, Canada, July, 2007.
"A Topology Design Customization Approach for (STNoC)",
Nano-Nets 07, in proceedings of 2nd International Conference on Nano-Networks (Nano-Nets 2007)., Catania, Italy, September 24-26, 2007.
"Response Surface Modeling for Embedded System Design Space Exploration",
Multi-objective design space exploration of multiprocessor SoC architectures: the MULTICUBE approach, New York, USA, Springer, 2011.
"Application-Specific Topology Design Customization for STNoC",
DSD07, in proceedings of 10th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD 07), Lübeck, Germany, August 29-31, 2007.
"Rapid Creation of Application Models from Bandwidth Aware Core Graphs",
Proceedings of: IP Based SoC Design 2007, Grenoble, France, December 5-6, 2007.
"Lattice-based cryptography: From reconfigurable hardware to ASIC",
2016 International Symposium on Integrated Circuits (ISIC): IEEE, 12/2016.
"Special Session Paper: Efficient Arithmetic for lattice-based Cryptography",
Proceedings of the CODES+ISSS 2017, 2017.
"Secure architectures of future emerging cryptography",
International Conference on Computing Frontiers CF'16, Como, italy, ACM New York, pp. 315-322, 05/2016.
"The ALaRI Intranet: a Remote Collaboration Platform for a Worldwide Learning and Research Network",
World Conference on Educational Multimedia, Hypermedia and Telecommunications 04 (ED-MEDIA 04), Lugano, Switzerland, AACE Press, pp. 5042-5047, 2004.
"FSM–based power modeling of wireless protocols: the case of bluetooth",
ISLPED '04: Proceedings of the 2004 international symposium on Low power electronics and design, Newport Beach, California, USA, ACM Press, New York, USA, pp. 369-374, 2004.
"Power/Performance Tradeoffs in Bluetooth Sensor Networks",
HICSS '06: Proceedings of the 39th Annual Hawaii International Conference on System Sciences, Washington, DC, USA, IEEE Computer Society, pp. 236.2, 2006.
"Flexible Power Modeling for Wireless Systems: Power Modeling and Optimization of two Bluetooth Implementations",
WOWMOM '05: Proceedings of the Sixth IEEE International Symposium on a World of Wireless Mobile and Multimedia Networks (WoWMoM'05), Washington, DC, USA, IEEE Computer Society, pp. 408–416, 2005.
"HardwareScheduling Support in SMP Architecture",
Design, Automation and Test in Europe(DATE), Nice, France, April 16-20, 2007.
"MDE Support for HW/SW Codesign: a UML-based Design Flow",
Advances in Design Methods from Modeling Languages for Embedded Systems and SoC's, Dordrecht, The Netherlands, Springer, pp. 19-37, 2010.
"Semi-Automated HW/SW Co-design for Embedded Systems: from MARTE Models to SystemC Simulators",
FDL'09 Proceedings, Sophia-Antipolis, France, September 22-24, 2009.
"Ultra-low power optimizations for the IEEE 802.15.4 networking protocol",
proceedings of MASS, October, 2007.
"Power Modeling and Power Analysis for IEEE 802.15.4: a Concurrent State Machine Approach",
Proceedings of CCNC 2007, Las Vegas, USA, January 11-13, 2007.
"Modelling the Power Cost of Security in Wireless Sensor Networks : the Case of 802.15.4",
Proceedings of IEEE ICT08, Saint Petersburg, Russia, June, 2008.
"Model-based Design Space Exploration for RTES with SysML and MARTE",
Proceedings of FDL08, Stuttgart, Germany, September, 2008.