Export 105 results:
Author Title [ Type
] Year Filters: Author is Francesco Regazzoni [Clear All Filters]
"TAO: Techniques for Algorithmic Obscuration during High-Level Synthesis",
Proceedings of the ACM/IEEE Design Automation Conference (DAC), 2018.
"(THOR) - The hardware onion router",
24th International Conference on Field Programmable Logic and Applications, (FPL) 2014, Munich, Germany, IEEE, 09/2014.
"Trojans in Early Design Steps - An Emerging Threat",
TRUDEVICE Final Conference (FCTRUâ16), 2016.
"Automatic Application of Power Analysis Countermeasures",
IEEE Transactions on Computers , vol. 64, issue 2, pp. 329-341, 02/2015.
"Automatic Application of Power Analysis Countermeasures",
IEEE Transactions on Computers, vol. PP, issue 99, 12/2013.
"Black-Hat High-Level Synthesis: Myth or Reality?",
IEEE Transactions on Very Large Scale Integration Systems, In Press.
"Breaking ECC2K-130",
IACR Cryptology ePrint Archive, vol. 2009, pp. 541, 11/2009.
"A Combined Design-Time/Test-Time Study of the Vulnerability of Sub-Threshold Devices to Low Voltage Fault Attacks",
IEEE Transactions on Emerging Topics in Computing, vol. PP, issue 99, 04/2014.
"Compact Circuits for Combined AES",
Journal of Cryptographic Engineering, In Press.
"Customized Instructions for Protection Against Memory Integrity Attacks",
IEEE Embedded Systems Letters, In Press.
"Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology",
Springer Transactions on Computational Science, vol. 5430, pp. 230–243, February, 2009.
"Exploring Energy Efficiency of Lightweight Block Ciphers",
(IACR) Cryptology ePrint Archive, vol. 2015, 09/2015.
"A Fast ULV Logic Synthesis Flow in Many-Vt CMOS Processes for Minimum Energy Under Timing Constraints",
IEEE Transactions on Circuits and Systems II: Express Briefs , vol. 59-II, issue 12, pp. 947-951, 02/2012.
"A Fast ULV Logic Synthesis Flow in Many-Vt CMOS Processes for Minimum Energy under Timing Constraints",
IEEE Transactions on Circuits and Systems II, vol. 59, issue 12, pp. 947-951, 2013.
"Harvesting the potential of nano-CMOS for lightweight cryptography: An ultra-low-voltage 65 nm AES coprocessor for passive RFID tags",
Springer Journal of Cryptographic Engineering, vol. 1, issue 1, 2011.
"An Investigation of Sources of Randomness Within Discrete Gaussian Sampling",
IACR Cryptology ePrint Archive, vol. 2017, pp. 298, 2017.
"Midori: (A) Block Cipher for Low Energy (Extended Version)",
(IACR) Cryptology ePrint Archive, vol. 2015, 12/2015.
"On Practical Discrete Gaussian Samplers For Lattice-Based Cryptography",
IEEE Transaction on Computers, In Press.
"Securing Hardware Accelerators: a New Challenge for High-Level Synthesis",
IEEE Embedded Systems Letters, vol. 3, issue 10, pp. 77-80, 11/2017, 2018.
"Simulation-Time Security Margin Assessment against Power-Based Side Channel Attacks",
(IACR) Cryptology ePrint Archive, vol. 2014, 05/2014.