Export 131 results:
Author [ Title] Type Year Filters: First Letter Of Last Name is S [Clear All Filters]
"An industrial design space exploration framework for supporting run-time resource management on multi-core systems",
Proceedings of Design, Automation and Test in Europe (DATE) Conference, Dresden, Germany, March, 2010.
"An Instruction-Level Methodology for Power Estimation and Optimization of Embedded VLIW cores",
DATE 2002, Paris, pp. 1128, March 4-8, 2002.
"An Instruction-Level Methodology for Power Estimation and Optimization of Embedded VLIW cores",
DATE 2002, Paris, pp. 1128, March 4-8, 2002.
"An Instruction-Level Methodology for Power Estimation and Optimization of Embedded VLIW cores",
DATE 2002, Paris, pp. 1128, March 4-8, 2002.
"An Investigation of Sources of Randomness Within Discrete Gaussian Sampling",
IACR Cryptology ePrint Archive, vol. 2017, pp. 298, 2017.
"Jailbreak Imagers: Transforming a Single-Photon Image Sensor into a True Random Number Generator",
International Image Sensor Workshop (IISW), Snowbird Resort, Utah, USA, June, 2013.
"Learning in Nonstationary Environments: A Hybrid Approach",
Artificial Intelligence and Soft Computing, Cham, Springer International Publishing, 2017.
"Linking run-time management with design space exploration at multiple abstraction levels",
Proceedings of the DATE'10 workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications, Dresden, Germany, March, 2010.
"Linking run-time resource management of embedded multi-core platforms with automated design-time exploration",
IET Computers and Digital Techniques, vol. 5, no. -, pp. 123–135, 2011.
"Low Cost FPGA Implementations of the SHA-3 Finalists",
10th Smart Card Research and Advanced Application Conference (CARDIS), Leuven, Belgium, September, 2011.
"Mapping and Topology Customization Approaches for Application-Specific STNoC Designs",
IEEE Proceedings of ASAP'07 - 18th International Conference on Application-specific Systems, Architectures and Processors, Montréal, Québec, Canada, July, 2007.
"Meta-model Assisted Optimization for Design Space Exploration of Multi-Processor Systems-on-Chip",
Euromicro Proceedings of DSD'09 - Conference on Digital System Design, Patras, Greece, August, 2009.
"A Methodology for efficient architectural exploration of energy-delay trade-offs for embedded systems",
SAC 2003, Melbourne, pp. 672-678, March, 2003.
"A Methodology for efficient architectural exploration of energy-delay trade-offs for embedded systems",
SAC 2003, Melbourne, pp. 672-678, March, 2003.
"A Methodology for efficient architectural exploration of energy-delay trade-offs for embedded systems",
SAC 2003, Melbourne, pp. 672-678, March, 2003.
"A Methodology for efficient architectural exploration of energy-delay trade-offs for embedded systems",
SAC 2003, Melbourne, pp. 672-678, March, 2003.
"Middleware Approaches for Adaptivity of Kahn Process Networks on Networks-on-Chip",
DASIP'11: Proceedings of the Conference on Design and Architectures for Signal and Image Processing, Tampere, Finland, pp. 1–8, November 2-4, 2011.
"Midori: A Block Cipher for Low Energy",
21st International Conference on the Theory and Application of Cryptology and Information Security ASIACRYPT 2015, vol. 9453, Auckland, New Zealand, Springer Berlin Heidelberg, pp. 411-436, 11/2015.
"Midori: (A) Block Cipher for Low Energy (Extended Version)",
(IACR) Cryptology ePrint Archive, vol. 2015, 12/2015.
"Modelling the Power Cost of Security in Wireless Sensor Networks : the Case of 802.15.4",
Proceedings of IEEE ICT08, Saint Petersburg, Russia, June, 2008.