Export 174 results:
Author [ Title
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"Compact Circuits for Combined AES",
Journal of Cryptographic Engineering, In Press.
"Compact Circuits for Combined AES",
Journal of Cryptographic Engineering, In Press.
"Compact Implementation and Performance Evaluation of Hash Functions in ATtiny Devices",
11th Smart Card Research and Advanced Application Conference (CARDIS), Graz, Austria, November, 2012.
"Comparison of Two Cameras based on Single Photon Avalanche Diodes (SPADS) for Fluorescence Lifetime Imaging Application with Picosecond Resolution",
International Image Sensor Workshop (IISW), Snowbird Resort, Utah, USA, June, 2013.
"Comparison of Two Cameras based on Single Photon Avalanche Diodes (SPADS) for Fluorescence Lifetime Imaging Application with Picosecond Resolution",
International Image Sensor Workshop (IISW), Snowbird Resort, Utah, USA, June, 2013.
"COOPER: Towards A Collaborative Open Environment of Project-centred Learning",
proceedings to EC-TEL'06 conference, Crete, Greece, October 1-4, 2006.
"COOPER: Towards A Collaborative Open Environment of Project-centred Learning",
proceedings to EC-TEL'06 conference, Crete, Greece, October 1-4, 2006.
"A Correlation-based Design Space Exploration Methodology for Multi-Processor Systems-on-Chip",
Proceedings of DAC 2010: Design Automation Conference, Anheim, CA, USA, pp. 120–125, June, 2010.
"Creating an Embedded Systems Program from Scratch: Nine years of experience at ALaRI",
Proceedings of the 2009 Workshop on Embedded System Education, Grenoble, France, October, 2009.
"Credit Card Fraud Detection: A Realistic Modeling and a Novel Learning Strategy",
IEEE Transactions on Neural Networks and Learning Systems, pp. 1-14, 2018.
"Credit Card Fraud Detection: A Realistic Modeling and a Novel Learning Strategy",
IEEE Transactions on Neural Networks and Learning Systems, pp. 1-14, 2018.
"Critical echo state network dynamics by means of Fisher information maximization",
2017 International Joint Conference on Neural Networks (IJCNN), May, 2017.
"Customized Instructions for Protection Against Memory Integrity Attacks",
IEEE Embedded Systems Letters, In Press.
"Design and Synthesis of Reusable Platforms with Programmable Interconnects",
UML-SoC 2005, Anaheim, California, pp. 43-48, June 12, 2005.
"A Design Flow and Evaluation Framework for DPA-resistant Instruction Set Extensions",
Cryptographic Hardware and Embedded Systems (CHES), vol. 5747, Lausanne, Switzerland, Springer Berlin Heidelberg, pp. 205-219, September, 2009.
"A Design Flow and Evaluation Framework for DPA-resistant Instruction Set Extensions",
Cryptographic Hardware and Embedded Systems (CHES), vol. 5747, Lausanne, Switzerland, Springer Berlin Heidelberg, pp. 205-219, September, 2009.
"Design Space Exploration of Parallel Architectures",
Multi-objective design space exploration of multiprocessor SoC architectures: the MULTICUBE approach, New York, USA, Springer, 2011.
"Determination of the Edge of Criticality in Echo State Networks Through Fisher Information Maximization",
IEEE Transactions on Neural Networks and Learning Systems, vol. 29, pp. 706-717, March, 2018.
"Development cost and size estimation starting from high-level specifications",
CODES '01: Proceedings of the ninth international symposium on Hardware/software codesign, Copenhagen, Denmark, ACM Press, New York, USA, pp. 86-91, 2001.
"DRuiD: Designing Reconfigurable Architectures with Decision-making Support",
19th Asia and South Pacific Design Automation Conference (ASP-DAC), Singapore, 01/2014.