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"OSCAR: an Optimization Methodology Exploiting Spatial Correlation in Multi-core Design Space", IEEE Transactions on Computer-Aided Design, vol. 21, issue 5, no. -: IEEE, pp. 740-753, 05/2012.
"ARTE: an Application-specific Run-Time Management Framework for Multi-core Systems", Proceedings IEEE SASP'11 - Symposium on Application Specific Processors, San Diego, CA, USA, June, 2011.
"DRuiD: Designing Reconfigurable Architectures with Decision-making Support", 19th Asia and South Pacific Design Automation Conference (ASP-DAC), Singapore, 01/2014.
"A Design Space Exploration Methodology Supporting Run-Time Resource Management for Multi-Processors System on-Chip", Proceedings IEEE SASP'09 - Symposium on Application Specific Processors, San Francisco, CA, USA, July, 2009.
"Using Multi-objective Design Space Exploration to Enable Run-time Resource Management for Reconfigurable Architectures", Proc. Design, Automation Test in Europe Conf. Exhibition (DATE), March, 2012.
"Multiprocessor System-on-Chip Design Space Exploration based on Multi-level Modeling Techniques", Proceedings of IEEE IC-SAMOS'09 - International Conference on Embedded Computer Systems: Architectures, MOdeling, and Simulation, Samos, Greece, July, 2009.
"Design-space Exploration and Runtime Resource Management for Multicores", ACM Transactions on Embedded Computing Systems (TECS) - Special issue on application-specific processors, vol. 13, issue 2, pp. 20:1–20:27, 09/2013.
"An industrial design space exploration framework for supporting run-time resource management on multi-core systems", Proceedings of Design, Automation and Test in Europe (DATE) Conference, Dresden, Germany, March, 2010.
"Multicube Explorer - A Design Space Exploration Framework for Embedded Systems-on-Chip", Proceedings of the DATE'09 workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications, Nice, France, April, 2009.
"Design Space Exploration of a Reconfigurable System for Supporting Video Streaming Run-time Management", Multi-objective design space exploration of multiprocessor SoC architectures: the MULTICUBE approach, New York, USA, Springer, 2011.
"Design Space Exploration for Run-Time Management of a Reconfigurable System for Video Streaming", Multi-objective design space exploration of multiprocessor SoC architectures: the MULTICUBE approach, 1: Springer, pp. 189-204, 2011.
"Securability: the Key Challenge for Autonomic and Trusted Computing", IEEE International Conference on Ubiquitous Intelligence Computing / International Conference on Autonomic Trusted Computing (UIC/ATC), 9, 03/2012.
"Predictive Analytics: A Shortcut to Dependable Computing", Software Engineering for Resilient Systems, Cham, Springer International Publishing, 2017.
"Design Space Exploration of PISA Architecture For ONU Auto-discovery Process", proceedings of 6th International Conference of Electrical Engineering (ICEENG), Cairo, Egypt, May 27-29, 2009.
"Quasi-Pipelined Hash Circuits", IEEE ARITH 17, Cape Cod, pp. 222-229, June, 2005.
Method of implementing one-to-one binary function and relative hardware device, especially for a Rijndael S-box, , no. US 10/816,791 -- EP 20030425211, 10/2004.
Method and circuit for data encryption/decryption, , no. US 09/974,705, April, 2003.
"ASIC Hardware Implementation of the IDEA NXT Encryption Algorithm", IEEE International Symposium on Circuits and Systems, Kos, Greece, May 21-24, 2006.
"Hardware Implementation of the Rijndael Sbox: a Case Study", ST Journal of System Research, pp. 84-91, July, 2003.
"Small-scale Variants of the Secure Hash Standard", ECRYPT workshop on RFID and lightweight cryptography, Graz, Austria, July 14-15, 2005.