Export 106 results:
Author Title [ Type
] Year Filters: First Letter Of Last Name is F [Clear All Filters]
"An Automated Design Flow for NoC-based MPSoCs on FPGA",
RSP 2008, The 19th IEEE/IFIP International Symposium on Rapid System Prototyping, Monterey, USA/CA, June 2-5, 2008.
"Can we Achieve both Privacy Protection and Efficient Malware Detection on Smartphones?",
1st Interdisciplinary Cyber Research Workshop 2015, Tallin, Estona, Tallinn University of Technology, 07/2015.
"The Certicom Challenges ECC2-X",
Workshop on Special Purpose Hardware for Attacking Cryptographic Systems (SHARCS), Lausanne, Switzerland, September, 2009.
"Challenges in designing trustworthy cryptographic co-processors",
IEEE International Symposium on Circuits and Systems (ISCAS) 2015, Lisbon, Portugal, IEEE, pp. 2009-2012, 09/2015.
"Cross-layer Design of Reconfigurable Cyber-Physical Systems",
Proceedings of Design, Automation and Test in Europe (DATE) 2017, 2017.
"A Data protection Unit for NoC-based Architecture",
CODES+ISSS 2007, in proceedings of the Fifth IEEE/ACM/FIP International Conference of Hardware/Software Codesign and System Synthesis (CODES+ISSS 2007), Salzburg, Austria, September 30, 2007.
"Design exploration for an Ogg/Vorbis decoder for VLIW architectures",
Workshop on Application Specific Processors (WASP '07), Salzburg, Austria, October, 2007.
"Design methodologies for securing cyber-physical systems",
2015 International Conference on Hardware/Software Codesign and System Synthesis CODES+ISSS, Amsterdam, Netherlands, IEEE, pp. 30-36, 10/2015.
"Design of Fault Tolerant Network Interfaces for NoCs",
Proceedings of 14th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD'11), Oulu, Finland, September, 2011.
"Design Space Exploration of PISA Architecture For ONU Auto-discovery Process",
proceedings of 6th International Conference of Electrical Engineering (ICEENG), Cairo, Egypt, May 27-29, 2009.
"Detecting changes at the sensor level in cyber-physical systems: Methodology and technological implementation",
2017 International Joint Conference on Neural Networks (IJCNN), May, 2017.
"Development cost and size estimation starting from high-level specifications",
CODES '01: Proceedings of the ninth international symposium on Hardware/software codesign, Copenhagen, Denmark, ACM Press, New York, USA, pp. 86-91, 2001.
"Efficient C implementation of the ECC and AES cryptographic systems",
Technology Leadership Day - organized by the MicroSwiss Network, Fribourg, October 10, 2001.
"Efficient Software Implementation of AES on 32-Bit Platforms",
CHES '02: Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems, London, UK, Springer-Verlag, pp. 159–171, 2003.
"Evaluating the Impact of Environmental Factors on Physically Unclonable Functions",
International Symposium on Field-Programmable Gate Arrays FPGA 2016, Monterey, CA, USA, ACM New York, NY, USA, pp. 279, 02/2016.
"A Framework for Security and Workload Gradual Adaptation",
SECRYPT, Seville, Spain, ICETE, 07/2011.
"A Friend or a Foe? Detecting Malware Using Memory and CPU Features",
SECRYPT 2016, 13th International Conference on Security and Cryptography, Lisbon, Portugal, SciTePress Digital Library, 07/2016.
"Gradual Adaptation of Security for Sensor Networks",
IEEE WoWMoM 2010: Proceedings of the IEEE International Symposium on a World of Wireless Mobile and Multimedia Networks, Montreal, Canada, June 13, 2010.
"Hardware-assisted Security Enhanced Linux in Embedded Systems: a Proposal",
Proceedings of the 5th Workshop on Embedded Systems Security (WESS'2010), Scottsdale, Arizona, USA, October 24, 2010.
"Hardware-assisted Security Enhanced Linux in Embedded Systems: a Proposal",
Proceedings of the 5th Workshop on Embedded Systems Security (WESS'2010), Scottsdale, Arizona, USA, October 24, 2010.