Export 144 results:
Author [ Title
] Type Year Filters: First Letter Of Last Name is R [Clear All Filters]
"Compact Circuits for Combined AES",
Journal of Cryptographic Engineering, In Press.
"Compact Implementation and Performance Evaluation of Block Ciphers in ATtiny Devices",
Progress in Cryptology - Africacrypt, Ifrance, Morocco, July, 2012.
"Compact Implementation and Performance Evaluation of Hash Functions in ATtiny Devices",
11th Smart Card Research and Advanced Application Conference (CARDIS), Graz, Austria, November, 2012.
"Compact, Scalable, and Efficient Gaussian Samplers for Lattice-Based Cryptography",
Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS) 2018, 2018.
"Compact, Scalable, and Efficient Gaussian Samplers for Lattice-Based Cryptography",
Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS) 2018, 2018.
"Comparison of Two Cameras based on Single Photon Avalanche Diodes (SPADS) for Fluorescence Lifetime Imaging Application with Picosecond Resolution",
International Image Sensor Workshop (IISW), Snowbird Resort, Utah, USA, June, 2013.
"Cross-layer Design of Reconfigurable Cyber-Physical Systems",
Proceedings of Design, Automation and Test in Europe (DATE) 2017, 2017.
"Cross-layer Design of Reconfigurable Cyber-Physical Systems",
Proceedings of Design, Automation and Test in Europe (DATE) 2017, 2017.
"Customized Instructions for Protection Against Memory Integrity Attacks",
IEEE Embedded Systems Letters, In Press.
"Customized Instructions for Protection Against Memory Integrity Attacks",
IEEE Embedded Systems Letters, In Press.
"A Design Flow and Evaluation Framework for DPA-resistant Instruction Set Extensions",
Cryptographic Hardware and Embedded Systems (CHES), vol. 5747, Lausanne, Switzerland, Springer Berlin Heidelberg, pp. 205-219, September, 2009.
"Design methodologies for securing cyber-physical systems",
2015 International Conference on Hardware/Software Codesign and System Synthesis CODES+ISSS, Amsterdam, Netherlands, IEEE, pp. 30-36, 10/2015.
"The design space of the number theoretic transform: A survey",
2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, {SAMOS} 2017, Pythagorion, Greece, July 17-20, 2017 (Invited), 2017.
"Detecting changes at the sensor level in cyber-physical systems: Methodology and technological implementation",
2017 International Joint Conference on Neural Networks (IJCNN), May, 2017.
"An eda-friendly protection scheme against side-channel attacks",
Design, Automation and Test in Europe (DATE), Grenoble, France, March, 2013.
"Efficient Configurations for Block Ciphers with Unified ENC/DEC Paths",
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust (HOST) 2017, 2018.
"Embedded Systems Education: Job Market Expectations",
Workshop on Embedded and Cyber-Physical Systems Education (WESE) , New Delhi, India, ACM, 10/2014.
"Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology",
Springer Transactions on Computational Science, vol. 5430, pp. 230–243, February, 2009.
"Evaluating the Impact of Environmental Factors on Physically Unclonable Functions",
International Symposium on Field-Programmable Gate Arrays FPGA 2016, Monterey, CA, USA, ACM New York, NY, USA, pp. 279, 02/2016.
"Exploring Energy Efficiency of Lightweight Block Ciphers",
(IACR) Cryptology ePrint Archive, vol. 2015, 09/2015.