Export 60 results:
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"Meta-model Assisted Optimization for Design Space Exploration of Multi-Processor Systems-on-Chip",
Euromicro Proceedings of DSD'09 - Conference on Digital System Design, Patras, Greece, August, 2009.
"ARTE: an Application-specific Run-Time Management Framework for Multi-cores based on Queuing Models",
Parallel Computing, 2013.
"Run-time Optimization of a Dynamically Reconfigurable Embedded System Through Performance Prediction",
23rd International Conference on Field Programmable Logic and Applications (FPL), Porto, Portugal, IEEE, 09/2013.
"A Correlation-based Design Space Exploration Methodology for Multi-Processor Systems-on-Chip",
Proceedings of DAC 2010: Design Automation Conference, Anheim, CA, USA, pp. 120–125, June, 2010.
"Evaluating Run-time Resource Management Policies for Multi-core Embedded Platforms with the EMME Evaluation Framework",
Workshop on Parallel Programming and Run-time Management Techniques for Many-core Architectures, February, 2012.
"OSCAR: an Optimization Methodology Exploiting Spatial Correlation in Multi-core Design Space",
IEEE Transactions on Computer-Aided Design, vol. 21, issue 5, no. -: IEEE, pp. 740-753, 05/2012.
"ARTE: an Application-specific Run-Time Management Framework for Multi-core Systems",
Proceedings IEEE SASP'11 - Symposium on Application Specific Processors, San Diego, CA, USA, June, 2011.
"Cross-layer Design of Reconfigurable Cyber-Physical Systems",
Proceedings of Design, Automation and Test in Europe (DATE) 2017, 2017.
"Fresh Re-Keying: Security against Side-Channel and Fault Attacks for Low-Cost Devices",
Proceedings of Progress in Cryptology - Africacrypt, Stellenbosch, South Africa, May, 2010.
"Fresh Re-Keying II: Securing Multiple Parties against Side-Channel and Fault Attacks",
10th Smart Card Research and Advanced Application Conference (CARDIS), Leuven, Belgium, September, 2011.
"System Adaptivity and Fault-tolerance in NoC-based MPSoCs: the MADNESS Project Approach",
Proceedings of the 15th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD'12), Izmir, Turkey, September 5-8, 2012.
Reconfigurable Logic Circuit,
, no. GB1719355.8, 11/2017, Submitted.
"Rethinking Secure FPGAs: TowardsCryptography-friendly Configurable Cell Architecture and its Automated Design Flow",
Proceedings of FCCM, 05/2018.
"NPART - node placement algorithm for realistic topologies in wireless multihop network simulation",
Proceedings of the 2nd International Conference on Simulation Tools and Techniques, ICST, Brussels, Belgium, Belgium, ICST (Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering), 2009.
"Can we Achieve both Privacy Protection and Efficient Malware Detection on Smartphones?",
1st Interdisciplinary Cyber Research Workshop 2015, Tallin, Estona, Tallinn University of Technology, 07/2015.
"Malware Threats and Solutions for Trustworthy Mobile Systems Design",
Hardware Security and Trust: Design and Deployment of Integrated Circuits in a Threatened Environment, First edition; 2016: Springer, pp. 149-167, 2017.
"MalAware: Effective and Efficient Run-time Mobile Malware Detector",
The 14th IEEE International Conference on Dependable, Autonomic and Secure Computing (DASC 2016), Auckland, New Zealand, IEEE Computer Society Press, 08/2016.
"A Resource-optimized Approach to Efficient Early Detection of Mobile Malware",
3rd International Workshop on Security of Mobile Applications - IWSMA 2014, Fribourg, Switzerland, 09/2014.
"Runtime Classification of Mobile Malware for Resource-constrained Devices",
Lecture Notes in Communications in Computer and Information Science, vol. 764: Springer International Publishing AG, pp. 195-215, 2017.
"Security Challenges for Hardware Designers of Mobile Systems",
2015 Mobile Systems Technologies Workshop (MST), May, 2015.