Export 61 results:
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] Title Type Year Filters: First Letter Of Last Name is B [Clear All Filters]
"Critical echo state network dynamics by means of Fisher information maximization",
2017 International Joint Conference on Neural Networks (IJCNN), May, 2017.
"Malicious Wave: a Survey on Actively Tampering Using Electromagnetic Glitch",
International Symposium on Electromagnetic Compatibility 2014, 08/2014.
"A survey on hardware trojan detection techniques",
IEEE International Symposium on Circuits and Systems (ISCAS) 2015, 2015, Lisbon, Portugal, IEEE, pp. 2021-2024, 08/2015.
"A 640 Mbit/s 32-bit Pipelined Implementation of the AES Algorithm",
SECRYPT, Porto, Portugal, July 26, 2008.
"Efficient Software Implementation of AES on 32-Bit Platforms",
CHES '02: Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems, London, UK, Springer-Verlag, pp. 159–171, 2003.
"Speeding Up AES By Extending a 32 bit Processor Instruction Set",
ASAP '06: Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06), Washington, DC, USA, IEEE Computer Society, pp. 275-282, 2006.
"Evaluating the Impact of Environmental Factors on Physically Unclonable Functions",
International Symposium on Field-Programmable Gate Arrays FPGA 2016, Monterey, CA, USA, ACM New York, NY, USA, pp. 279, 02/2016.
"Stealthy Dopant-Level Hardware Trojans",
Workshop on Cryptographic Hardware and Embedded Systems (CHES), Santa Barbara, California, USA, August, 2013.
"Stealthy Dopant-Level Hardware Trojans: Extended Version",
Journal of Cryptographic Engineering, vol. 4, issue 1, pp. 19-31, 04/2014.
"Automatic Application of Power Analysis Countermeasures",
IEEE Transactions on Computers , vol. 64, issue 2, pp. 329-341, 02/2015.
"Sleuth: Automated Verification of Software Power Analysis Countermeasures",
Workshop on Cryptographic Hardware and Embedded Systems (CHES), Santa Barbara, California, USA, August, 2013.
"An eda-friendly protection scheme against side-channel attacks",
Design, Automation and Test in Europe (DATE), Grenoble, France, March, 2013.
"Automatic Application of Power Analysis Countermeasures",
IEEE Transactions on Computers, vol. PP, issue 99, 12/2013.
"A First Step Towards Automatic Application of Power Analysis Countermeasures",
48th Design Automation Conference (DAC), San Diego, Califorina, June, 2011.
"A Methodology for Bridging the Gap between UML and Codesign",
UML for SOC Design, Dordrecht, The Netherlands, Springer, pp. 119-146, 2005.
"Design and Synthesis of Reusable Platforms with Programmable Interconnects",
UML-SoC 2005, Anaheim, California, pp. 43-48, June 12, 2005.
"UML in an Electronic System Level Design Methodology",
UML-SOC'04, San Diego, California, pp. 47-52, June 6, 2004.
"Simulation-Time Security Margin Assessment against power-based Side Channel Attacks",
7th Workshop on Embedded Systems Security (WESS), Tampere, Finland, October, 2012.
"Low Cost Software Countermeasures Against Fault Attacks: Implementation and Performances Trade Offs",
5th Workshop on Embedded Systems Security (WESS), Scottsdale, Arizona, USA, October, 2010.
"Simulation-Time Security Margin Assessment against Power-Based Side Channel Attacks",
(IACR) Cryptology ePrint Archive, vol. 2014, 05/2014.