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Education and Innovation in Embedded Systems Design

USI Università della Svizzera italiana, USI Faculty of Informatics, Advanced Learning and Research Institute USI Università della Svizzera italiana USI Faculty of Informatics USI Advanced Learning and Research Institute
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Polian, I., G. Becker, and F. Regazzoni, "Trojans in Early Design Steps - An Emerging Threat", TRUDEVICE Final Conference (FCTRU’16), 2016.
Banik, S., V. Mikhalev, F. Armknecht, T. Isobe, W. Meier, A. Bogdanov, Y. Watanabe, and F. Regazzoni, "Towards Low Energy Stream Ciphers", IACR Transactions on Symmetric Cryptology, In Press.
Güneys, T., F. Regazzoni, P. Sasdrich, and M. Wojcik, "(THOR) - The hardware onion router", 24th International Conference on Field Programmable Logic and Applications, (FPL) 2014, Munich, Germany, IEEE, 09/2014.
Pilato, C., F. Regazzoni, R. Karri, and S. Garg, "TAO: Techniques for Algorithmic Obscuration during High-Level Synthesis", Proceedings of the ACM/IEEE Design Automation Conference (DAC), 2018.
Regazzoni, F., I. Bonesana, M. Djakov, and A. Mattiuz, "Tairona, an Open Source Platform for Worldwide Meeting and Tutoring", World Conference on Educational Multimedia, Hypermedia and Telecommunications 7 (ED-MEDIA 07), Vancouver, Canada, 2007.
Pilato, C., S. Garg, K. Wu, R. Karri, and F. Regazzoni, "TaintHLS: High-Level Synthesis For Dynamic Information Flow Tracking", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, In Press.
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Bhasin, S., and F. Regazzoni, "A survey on hardware trojan detection techniques", IEEE International Symposium on Circuits and Systems (ISCAS) 2015, 2015, Lisbon, Portugal, IEEE, pp. 2021-2024, 08/2015.
Becker, G., F. Regazzoni, C. Paar, and W. Burleson, "Stealthy Dopant-Level Hardware Trojans: Extended Version", Journal of Cryptographic Engineering, vol. 4, issue 1, pp. 19-31, 04/2014.
Becker, G., F. Regazzoni, C. Paar, and W. Burleson, "Stealthy Dopant-Level Hardware Trojans", Workshop on Cryptographic Hardware and Embedded Systems (CHES), Santa Barbara, California, USA, August, 2013.
Howe, J., C. Moore, M. O'Neill, F. Regazzoni, T. Güneysu, and K.. Beeden, "Standard lattices in hardware", Proceedings of the 53rd Annual Design Automation Conference DAC 2016, Austin, TX, USA, ACM, pp. 162, 06/2016.
Bertoni, G M., L. Breveglieri, R. Farina, and F. Regazzoni, "Speeding Up AES By Extending a 32 bit Processor Instruction Set", ASAP '06: Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06), Washington, DC, USA, IEEE Computer Society, pp. 275-282, 2006.
Sami, M., M. Macchetti, and F. Regazzoni, "Speeding Security on the Intel StrongARM", Embedded Intel Solutions, pp. 31-33, 2005.
O'Sullivan, E., and F. Regazzoni, "Special Session Paper: Efficient Arithmetic for lattice-based Cryptography", Proceedings of the CODES+ISSS 2017, 2017.
Bayrak, A. Galip, F. Regazzoni, D. Novo Bruna, and P. Ienne, "Sleuth: Automated Verification of Software Power Analysis Countermeasures", Workshop on Cryptographic Hardware and Embedded Systems (CHES), Santa Barbara, California, USA, August, 2013.
Charbon, E., and F. Regazzoni, "Single-Photon Image Sensors", Special Session, 50th Design Automation Conference (DAC), Austin, Texas, USA, June, 2013.
Regazzoni, F., S. Burri, D. Stucki, Y. Maruyama, C. Bruschini, and E. Charbon, "Single-Photon Avalanche Diodes (SPADs) for quantum random number generators and beyond", 19th Asia and South Pacific Design Automation Conference (ASP-DAC) 2014, Singapore, IEEE, 01/2014.
Barenghi, A., G. Pelosi, and F. Regazzoni, "Simulation-Time Security Margin Assessment against Power-Based Side Channel Attacks", (IACR) Cryptology ePrint Archive, vol. 2014, 05/2014.
Barenghi, A., G. Pelosi, and F. Regazzoni, "Simulation-Time Security Margin Assessment against power-based Side Channel Attacks", 7th Workshop on Embedded Systems Security (WESS), Tampere, Finland, October, 2012.
Regazzoni, F., S. Badel, T. Eisenbarth, J. Großschädl, A. Poschmann, Z. Toprak, M. Macchetti, L. Pozzi, C. Paar, Y. Leblebici, et al., "Simulation-based Methodology for Evaluating DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies", International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS IC 07), Samos, Greece, July 16-19, 2007.
Guo, X., N. Karimi, F. Regazzoni, C. Jin, and R. Karri, "Simulation and Analysis of Negative-Bias Temperature Instability Aging on Power Analysis Attacks", IEEE Int. Symposium on Hardware-Oriented Security and Trust, McLean, VA, USA, 05/2015.

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