@Patent {18589,
	title = {Reconfigurable Logic Circuit},
	number = {GB1719355.8},
	year = {Submitted},
	month = {11/2017},
	type = {UK},
	author = {Mentens, Nele and Charbon, Edoardo and Regazzoni, Francesco}
}
@conference {18575,
	title = {Rethinking Secure FPGAs: TowardsCryptography-friendly Configurable Cell Architecture and its Automated Design Flow},
	booktitle = {Proceedings of FCCM},
	year = {2018},
	month = {05/2018},
	author = {Mentens, Nele and Charbon, Edoardo and Regazzoni, Francesco}
}
@conference {18484,
	title = {Round gating for low energy block ciphers},
	booktitle = {2016 IEEE International Symposium on Hardware Oriented Security and Trust, HOST},
	year = {2016},
	month = {05/2016},
	pages = {55-60},
	publisher = {IEEE Computer Society},
	organization = {IEEE Computer Society},
	address = {McLean, VA, USA},
	abstract = {Pushed by the pervasive diffusion of devices operated by battery or by the energy harvested, energy has become one of the most important parameter to be optimized for embedded systems. Particularly relevant would be to optimize the energy consumption of security primitives. In this paper we explore design techniques for implementing block ciphers in a low energy fashion. We concentrate on round based implementation and we discuss how gating, applied at round level can affect and improve the energy consumption of the most common lightweight block cipher currently used in the internet of things. Additionally, we discuss how to needed gating wave can be generated. Experimental results show that our technique is able to reduce the energy consumption in most block ciphers by over 60\% while incurring only a minimal overhead in hardware},
	keywords = {algorithm design and analysis, ciphers, clocks, computer architecture, energy consumption},
	isbn = {978-1-4673-8826-9},
	doi = {10.1109/HST.2016.7495556},
	url = {http://dx.doi.org/10.1109/HST.2016.7495556},
	author = {Banik, Subhadeep and Bogdanov, Andrey and Regazzoni, Francesco and Isobe, Takanori and Hiwatari, Harunaga and Akishita, Toru}
}
@conference {116.TuRePaFeSc10,
	title = {A Reconfigurable Multiprocessor Architecture for a Reliable Face Recognition Implementation},
	booktitle = {Proceedings of Design, Automation and Test in Europe (DATE) Conference},
	year = {2010},
	month = {March},
	address = {Dresden, Germany},
	abstract = {Face Recognition techniques are solutions used to quickly screen a huge number of persons without being intrusive in open environments or to substitute id cards in companies or research institutes. There are several reasons that require to systems implementing these techniques to be reliable. This paper presents the design of a reliable face recognition system implemented on Field Programmable Gate Array (FPGA). The proposed implementation uses the concepts of multiprocessor architecture, parallel software and dynamic reconfiguration to satisfy the requirement of a reliable system. The target multiprocessor architecture is extended to support the dynamic reconfiguration of the processing unit to provide reliability to processors fault. The experimental results show that, due to the multiprocessor architecture, the parallel face recognition algorithm can achieve a speed up of 63\% with respect to the sequential version. Results regarding the overhead in maintaining a reliable architecture are also shown},
	author = {Tumeo, Antonino and Regazzoni, Francesco and Palermo, Gianluca and Ferrandi, Fabrizio and Sciuto, Donatella}
}
@conference {73.OtReLa07,
	title = {Rapid Creation of Application Models from Bandwidth Aware Core Graphs},
	booktitle = {Proceedings of: IP Based SoC Design 2007},
	year = {2007},
	month = {December 5-6},
	address = {Grenoble, France},
	abstract = {We present a methodology that allows rapid creation of application models from bandwidth aware core graphs that are available in the literature for a wide range of applications and we discuss their applicability to the rapid exploration of multiple Networks on Chip (NoCs) layout organizations. In a bandwidth aware core graph, each node represents a core and the numbers on the edges represent the bandwidth requirements between cores. We describe core graphs in a UML object model diagram and we then have an automatic code generation tool which produces a SystemC description whose behaviour results in a packet generation on every output connection that respects the bandwidth requirements specified in the core graph. We can then rapidly derive a NoC mapping in which a specific floorplan of the cores can be evaluated and compared with alternate floorplan options for rapid design space exploration.},
	keywords = {network-on-chip (NoC), rapid prototyping},
	author = {Otero, Jo{\~a}o and Regazzoni, Francesco and Lajolo, Marcello}
}
