@article {18569,
	title = {Compact Circuits for Combined AES},
	journal = {Journal of Cryptographic Engineering},
	year = {In Press},
	author = {Banik, Subhadeep and Bogdanov, Andrey and Regazzoni, Francesco}
}
@article {18567,
	title = {Customized Instructions for Protection Against Memory Integrity Attacks},
	journal = {IEEE Embedded Systems Letters},
	year = {In Press},
	author = {Roy, Debapriya Basu and Alam, Manaar and Bhattacharya, Sarani and Govindan, Vidya and Regazzoni, Francesco and Chakraborty, Rajat Subhra and Mukhopadhyay, Debdeep}
}
@article {18549,
	title = {The Case for Polymorphic Registers in Dataflow Computing},
	journal = {International Journal of Parallel Programming},
	volume = {54},
	issue = {5},
	year = {2018},
	month = {10/2018},
	pages = {54-62},
	chapter = {54},
	doi = {10.1007/s10766-017-0494-1},
	author = {Ciobanu, Catalin B. and Gaydadjiev, Georgi and Pilato, Christian and Sciuto, Donatella}
}
@conference {18593,
	title = {A characterization of the Edge of Criticality in Binary Echo State Networks},
	booktitle = {2018 IEEE 28th International Workshop on Machine Learning for Signal Processing (MLSP)},
	year = {2018},
	month = {09/2018},
	address = {Aalborg, Denmark},
	author = {Verzelli, Pietro and Livi, Lorenzo and Alippi, Cesare}
}
@conference {18573,
	title = {Compact, Scalable, and Efficient Gaussian Samplers for Lattice-Based Cryptography},
	booktitle = {Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS) 2018},
	year = {2018},
	author = {Khalid, Ayesha and Howe, James and Rafferty, Ciara and Regazzoni, Francesco and O{\textquoteright}Neil, Maire}
}
@article {18545,
	title = {Concept Drift and Anomaly Detection in Graph Streams},
	journal = {IEEE Transactions on Neural Networks and Learning Systems},
	volume = {29},
	issue = {11},
	year = {2018},
	month = {11/2018},
	pages = {5592-5605},
	chapter = {5592},
	author = {Zambon, Daniele and Alippi, Cesare and Livi, Lorenzo}
}
@article {18536,
	title = {Credit Card Fraud Detection: A Realistic Modeling and a Novel Learning Strategy},
	journal = {IEEE Transactions on Neural Networks and Learning Systems},
	year = {2018},
	pages = {1-14},
	keywords = {Amplitude modulation, Area measurement, Companies, Concept drift, Credit card fraud detection, Credit cards, learning in nonstationary environments, Learning systems, Tools, Training, unbalanced classification.},
	issn = {2162-237X},
	doi = {10.1109/TNNLS.2017.2736643},
	author = {Dal Pozzolo, Andrea and Boracchi, Giacomo and Caelen, Olivier and Alippi, Cesare and Bontempi, Gianluca}
}
@conference {18538,
	title = {Critical echo state network dynamics by means of Fisher information maximization},
	booktitle = {2017 International Joint Conference on Neural Networks (IJCNN)},
	year = {2017},
	month = {May},
	keywords = {Asymptotic stability, critical phase transitions, echo state network, edge of criticality, Electronic mail, ESN, Estimation, estimation theory, FIM, Fisher information matrix, Fisher information maximization, hidden neurons activations, high short term memory capacity, input signal, low prediction error, network dynamics, network theory (graphs), Neurons, optimisation, Probability density function, recurrent neural nets, Reservoirs, signal processing, statistics, Tuning, unsupervised approach, unsupervised learning},
	doi = {10.1109/IJCNN.2017.7965941},
	author = {Bianchi, Filippo Maria and Livi, Lorenzo and Jenssen, Robert and Alippi, Cesare}
}
@conference {18581,
	title = {Cross-layer Design of Reconfigurable Cyber-Physical Systems},
	booktitle = {Proceedings of Design, Automation and Test in Europe (DATE) 2017},
	year = {2017},
	author = {Masin, Michael and Palumbo, Francesca and Myrhaug, Hans and Filho, Julio A. de Oliv and Pastena, Max and Pelcat, Maxime and Raffo, Luigi and Regazzoni, Francesco and Sanchez, Angel A. and Toffetti, Antonella and de la Torre, Eduardo and Zedda, Katiuscia}
}
@proceedings {18514,
	title = {CCM: Controlling the Change Magnitude in High Dimensional Data},
	journal = {In Proceedings of the 2nd INNS Conference on Big Data 2016 (INNS Big Data 2016)},
	year = {2016},
	month = {10/2016},
	pages = {1-10},
	address = {Thessaloniki, Greece},
	abstract = {Change-detection algorithms are often tested on real-world datasets where changes are synthetically introduced. While this common practice allows generating multiple datasets to obtain stable performance measures, it is often quite arbitrary since the change magnitude is seldom controlled. Thus, experiments { in particular those on multivariate and high-dimensional data. We here present a rigorous framework for introducing changes having a controlled magnitude in multivariate datasets. In particular, we introduce changes by directly roto-translating the data, and we measure the change magnitude by the symmetric
Kullback-Leibler divergence between pre- ad post-change distributions. We present an iterative algorithm that identities the roto-translation parameters yielding the desired change magnitude, and we prove its convergence analytically. We also illustrate our MATLAB framework that introduces changes having a controlled magnitude in real-world datasets, which is made publicly available for download.
},
	author = {Alippi, Cesare and Boracchi, Giacomo and Carrera, Diego}
}
@conference {18447,
	title = {Change Detection in Multivariate Datastreams: Likelihood and  Detectability Loss},
	booktitle = {25th International Joint Conference on Artificial Intelligence (IJCAI-16)},
	year = {2016},
	month = {07/2016},
	address = { New York, USA},
	abstract = {We address the problem of detecting changes in multivariate datastreams, and we investigate the intrinsic difficulty that change-detection methods have to face when the data-dimension scales. In particular, we consider the general approach that detects changes by comparing the distribution of the log-likelihood of the datastream over different time windows. Despite the fact that this approach constitutes the frame for several change-detection methods, its effectiveness when the dimension of data scales has never been investigated, which is indeed the goal of our paper. We show that the magnitude of the change can be naturally measured by the symmetric Kullback-Leibler divergence between the pre- and post-change distributions, and that the detectability of a change of a given magnitude worsens when the data-dimension increases. This structural problem, which we refer to as detectability loss, is due to the linear relationship existing between the variance of the log-likelihood and the data dimension, and reveals to be harmful even at low data-dimensions (say, 10). We analytically derive the detectability loss on Gaussian-distributed datastreams, and empirically demonstrate that this problem holds also on real-world datasets.},
	author = {Alippi, Cesare and Boracchi, Giacomo and Carrera, Diego and Roveri, Manuel}
}
@article {18511,
	title = {A Cloud to the Ground: The New Frontier of Intelligent and Autonomous Networks of Things},
	journal = {IEEE Communication Magazine},
	volume = {54},
	issue = {12},
	year = {2016},
	month = {11/2016},
	pages = {14 - 20},
	chapter = {14},
	abstract = {The Internet-of-Things (IoT) paradigm is supporting -and will support- an ever-increasing number of services and applications impacting on almost every aspect of our everyday life. The current trend is forecasting IoT to connect tens of billion objects by 2020 yielding a very-high volume of data to be acquired, transmitted and processed. IoT typically relies on Cloud Computing to process, analyze and store the data acquired by IoT entities. Unfortunately, the need to transmit all data from the information producing objects to the Cloud for a subsequent processing/analysis phase would require a large bandwidth and increase the latency in the {\textquotedblleft}decision-making process{\textquotedblright} whenever decisions/reactions must be promptly taken by the IoT units.
The Fog Computing (FC) paradigm aims at addressing these problems by extending Cloud Computing towards the edge of the network. In this direction, this paper introduces a novel FC-IoT paradigm designed
to move computing, storage and applications/services close to IoT objects so as to reduce communication bandwidth and energy consumption as well as {\textquotedblleft}decision-making{\textquotedblright} latency. The proposed IoT-based solution has been designed to have intelligent and autonomous IoT objects that are integrated with a FC and Fog Networking approach. The distinguishing features of the intelligent FC-IoT platform are low-latency, self-adaptation, low energy consumption and spectrum efficiency.
},
	doi = { 10.1109/MCOM.2016.1600541CM},
	author = {Alippi, Cesare and Fantacci, Romano and Marabissi, Dania and Roveri, Manuel}
}
@conference {18390,
	title = {Can we Achieve both Privacy Protection and Efficient Malware Detection on Smartphones?},
	booktitle = {1st Interdisciplinary Cyber Research Workshop 2015},
	year = {2015},
	month = {07/2015},
	publisher = {Tallinn University of Technology},
	organization = {Tallinn University of Technology},
	address = {Tallin, Estona},
	url = {http://cybercentre.cs.ttu.ee/wp/wp-content/uploads/2015/02/ICR_2015_proceedings.pdf},
	author = {Milosevic, Jelena and Ferrante, Alberto and Malek, Miroslaw}
}
@conference {18477,
	title = {Challenges in designing trustworthy cryptographic co-processors},
	booktitle = {IEEE International Symposium on Circuits and Systems (ISCAS) 2015},
	year = {2015},
	month = {09/2015},
	pages = {2009-2012},
	publisher = {IEEE},
	organization = {IEEE},
	address = {Lisbon, Portugal},
	abstract = {Security is becoming ubiquitous in our society. However, the vulnerability of electronic devices that implement the needed cryptographic primitives has become a major issue. This paper starts by presenting a comprehensive overview of the existing attacks to cryptography implementations. Thereafter, the state-of-the-art on some of the most critical aspects of designing cryptographic co-processors are presented. This analysis starts by considering the design of asymmetrical and symmetrical cryptographic primitives, followed by the discussion on the design and online testing of True Random Number Generation. To conclude, techniques for the detection of Hardware Trojans are also discussed},
	keywords = {asymmetrical cryptographic primitives, cryptography, hardware Trojan detection techniques},
	issn = {0271-4302 },
	doi = {10.1109/ISCAS.2015.7169070},
	url = {http://dx.doi.org/10.1109/ISCAS.2015.7169070},
	author = {Regazzoni, Francesco and Graves, Ricardo and Di Natale, Giorgio and Batina, Lejla and Bhasin, Shivam and Ege, Baris and Fournaris, Apostolos P. and Mentens, Nele and Picek, Stjepan and Rozic, Vladimir and Sklavos, Nicolas and Yang, Bohan}
}
@article {18058,
	title = {A Combined Design-Time/Test-Time Study of the Vulnerability of Sub-Threshold Devices to Low Voltage Fault Attacks},
	journal = {IEEE Transactions on Emerging Topics in Computing},
	volume = {PP},
	issue = {99},
	year = {2014},
	month = {04/2014},
	abstract = {The continuous scaling of VLSI technology and the possibility to run circuits in subthreshold voltage range make it possible to implement standard cryptographic primitives within the very limited circuit and power budget of RFID devices. However, such cryptographic implementations raise concerns regarding their vulnerability to both active and passive side-channel attacks. In particular, when focusing on RFID targeted designs, it is important to evaluate their resistance against low cost physical attacks. A low cost fault injection attack can be mounted, for example, by lowering the supply voltage of the chip with the goal of causing setup time violations. In this paper, we provide an in-depth characterization of a chip implementation of the AES cipher. The chip has been designed using a 65nm low power standard cell library and operates in a subthreshold voltage range. We first show that it is possible to inject faults (through lowering the supply voltage) compliant with the fault models required to perform attacks against the AES cipher. We then investigate the possibility of predicting, at design time, which parts of the chip are more likely to be sensitive to such fault injection attacks and produce the desirable (from the point of view of the attacker) faulty behavior. Identifying such sensitive logic signals allows us to suggest to the designer a tailored countermeasure strategy for thwarting these attacks, with a minimal impact on the circuit{\textquoteright}s performance.},
	issn = {2168-6750},
	doi = {10.1109/TETC.2014.2316509},
	author = {Barenghi, Alessandro and Hocquet, C{\'e}dric and Bol, David and Standaert, Fran{\c c}ois-Xavier and Regazzoni, Francesco and Koren, Israel}
}
@conference {18296,
	title = {A Conceptual Solution for Integration of EV Charging with Smart Grids },
	booktitle = {International Conference on Smart Grid and Clean Energy Technologies - ICSGCE 2014 },
	year = {2014},
	month = {10/2014},
	address = {Dubai},
	abstract = {Coordinated charging of electric vehicles (EVs) represents one of important aspects of future smart grid
implementation. The main focus of the present work is on designing a conceptual architecture as a solution for
managing (mobile) electric storages utilization. The solution requires holistic approach which takes into consideration
all actors in power system management. Requirements and use-cases are specified, structural and behavioral models
are developed and presented. The ICT (Information and Communication Technologies) model of the architecture that
supports smart charging with dynamic pricing is developed using systems engineering methods. Results are verified
by means of system level simulations.},
	keywords = {dynamic pricing, electric vehicles, Smart charging, systems engineering},
	author = {Lukovi{\'c}, Slobodan and Miladinovic, Bojan}
}
@conference {17741,
	title = {Calibration and in-Field Validation Tests of a Web-based Adaptive Management System for Monitoring - Scaphoideus titanus},
	booktitle = {Future Integrated Pest Management in Europe},
	year = {2013},
	abstract = {We developed a Web-based Adaptive Management System (WAMS) within a research project, called "SMART VINEYARD", which was funded by the Swiss Federal Commission for Technology and Innovation (Project 11307.1 PFES-ES). Goal of the project was to address the challenge of proposing a decision support system to provide real-time forecast of the life stages of - Scaphoideus titanus, vector of flavescence dor{\'e}e. The benefit of using the WAMS is to decide the timing of insecticide application and the planning of in-field monitoring tasks.},
	author = {Prevostini, Mauro and Taddeo, Antonio Vincenzo and Bala{\'c}, Katarina and Jermini, Mauro and Linder, Christian}
}
@conference {17768,
	title = {Characterization of In-tunnel Distance Measurements for Vehicle Localization},
	booktitle = {IEEE Wireless Communications and Networking Conference (WCNC)},
	year = {2013},
	address = {Shanghai, P.R. China},
	abstract = {An increased number of vehicular applications and services requires accurate distance measurements. Due to specific properties of radio waves propagation, it may not be effective to use ranging systems designed for other environments inside tunnels. In this paper we analysed the characteristics of time of flight based ranging for in-tunnel applications. Based on our analysis, we designed a vehicle localization system showing that the time of flight approach is a suitable, accurate and cost effective solution for this purpose. We designed and validated our solution by performing real experiments in a tunnel located in Lugano, Switzerland.},
	author = {Widmann, Daniel and Bala{\'c}, Katarina and Taddeo, Antonio Vincenzo and Prevostini, Mauro and Puiatti, Alessandro}
}
@conference {18069,
	title = {Comparison of Two Cameras based on Single Photon Avalanche Diodes (SPADS) for Fluorescence Lifetime Imaging Application with Picosecond Resolution},
	booktitle = {International Image Sensor Workshop (IISW)},
	year = {2013},
	month = {June},
	address = {Snowbird Resort, Utah, USA},
	author = {Powolny, Fran{\c c}ois and Burri, Samuel and Bruschini, Claudio and Michalet, Xavier and Regazzoni, Francesco and Charbon, Edoardo}
}
@article {18048,
	title = {A Configurable Monitoring Infrastructure for NoC-Based Architectures},
	journal = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
	volume = {PP},
	issue = {99},
	year = {2013},
	abstract = {In this brief, we propose a monitoring architecture for networks-on-chip that provides system information useful for designers to efficiently exploit, at design time and run-time, the system resources available in multiprocessor system-on-chip platforms. We focus on the analysis of the architectural details and design challenges of such a system, by describing powerful tools for monitoring information that can be used both at run-time for detecting dynamic changes in system behavior and at post-execution time for debugging and profiling of applications. This brief describes the design of the monitoring probes, together with the events detectable by them, and discusses an architecture for collecting, storing, and analyzing the information gathered during an application execution.},
	keywords = {hardware counters, networks-on-chip (NoCs), performance monitoring, systems-on-chip (SoCs).},
	issn = {1063-8210},
	doi = {10.1109/TVLSI.2013.2290102},
	author = {Fiorin, Leandro and Palermo, Gianluca and Silvano, Cristina}
}
@conference {18075,
	title = {Compact Implementation and Performance Evaluation of Block Ciphers in ATtiny Devices},
	booktitle = {Progress in Cryptology - Africacrypt},
	year = {2012},
	month = {July},
	address = {Ifrance, Morocco},
	author = {Eisenbarth, Thomas and Gong, Zheng and Gneysu, Tim and Heyse, Stefan and Indesteege, Sebastiaan and Kerckhof, St{\'e}phanie and Koeune, Francois and Nad, Tomislav and Plos, Thomas and Regazzoni, Francesco and Standaert, Fran{\c c}ois-Xavier and Oldenzeel, Loic Van Oldene}
}
@conference {18073,
	title = {Compact Implementation and Performance Evaluation of Hash Functions in ATtiny Devices},
	booktitle = {11th Smart Card Research and Advanced Application Conference (CARDIS)},
	year = {2012},
	month = {November},
	address = {Graz, Austria},
	author = {Balasch, Josep and Ege, Baris and Eisenbarth, Thomas and Grard, Benot and Gong, Zheng and Gneysu, Tim and Heyse, Stefan and Kerckhof, St{\'e}phanie and Koeune, Francois and Plos, Thomas and Poppelmann, Thomas and Regazzoni, Francesco and Standaert, Fran{\c c}ois-Xavier and Van Assche, Gilles and Van Keer, Ronny and Oldenzeel, Loic Van Oldene and von Maurich, Ingo}
}
@conference {126.MaPaZaBrJoSi11,
	title = {A Correlation-based Design Space Exploration Methodology for Multi-Processor Systems-on-Chip},
	booktitle = {Proceedings of DAC 2010: Design Automation Conference},
	year = {2010},
	month = {June},
	pages = {120{\textendash}125},
	address = {Anheim, CA, USA},
	abstract = {Given the increasing complexity of multi-processor systems-on-chip, a wide range of parameters must be tuned to find the best trade-offs in terms of the selected system figures of merit (such as energy, delay and area). This optimization phase is called Design Space Exploration (DSE) consisting of a Multi-Objective Optimization (MOO) problem. In this paper, we propose an iterative design space exploration methodology exploiting the statistical properties of known system configurations to infer, by means of a correlation-based analysis, the next design points to be analyzed with low-level simulations. In fact, the knowledge of few design points is used to predict the expected improvement of unknown configurations. We show that the correlation of the configurations within the multi-processor design space can be modeled successfully with analytical functions and, thus, speed up the overall exploration phase. This makes the proposed methodology a model-assisted heuristic that, for the first time, exploits the correlation about architectural configurations to converge to the solution of the multi-objective problem.},
	keywords = {design space exploration, kriging, multiprocessor system-on-chip (MPSoC), response surface},
	author = {Mariani, Giovanni and Palermo, Gianluca and Zaccaria, Vittorio and Brankovic, Aleksandar and Jovic, Jovana and Silvano, Cristina}
}
@conference {18084,
	title = {The Certicom Challenges ECC2-X},
	booktitle = {Workshop on Special Purpose Hardware for Attacking Cryptographic Systems (SHARCS)},
	year = {2009},
	month = {September},
	address = {Lausanne, Switzerland},
	author = {Bailey, Daniel V. and Baldwin, Brian and Batina, Lejla and Bernstein, Daniel J. and Birkner, Peter and Bos, Joppe W. and van Damme, Gauthier and de Meulenaer, Giacomo and Fan, Junfeng and Gurkaynak, Frank and G{\"u}neys, Tim and Kleinjung, Thorsten and Lange, Tanja and Mentens, Nele and Paar, Christof and Regazzoni, Francesco and Schwabe, Peter and Uhsadel, Leif}
}
@article {94.DeFeTa08,
	title = {Coordinated management of hardware and software self-adaptivity},
	journal = {Journal of Systems Architecture},
	volume = {55},
	number = {{3}},
	issue = {3},
	year = {2009},
	note = {{Challenges in self-adaptive computing (Selected papers from the Aether-Morpheus 2007 workshop), Accepted Manuscript, Available online 29 July 2008}},
	month = {03/2009},
	pages = {170 - 179},
	abstract = {Self-adaptivity is the capability of a system to adapt itself dynamically to achieve its goals. Self-adaptive systems will be widely used in the future both to efficiently use system resources and to ease the management of complex systems. The frameworks for self-adaptivity developed so far usually concentrate either on self-adaptive software or on self-adaptive hardware, but not both. In this paper, we propose a model of self-adaptive systems and we describe how to manage self-adaptivity at all levels (both hardware and software) by means of a decentralized control algorithm. The key advantage of decentralized control is in the simplicity of the local controllers. Simulation results are provided to show the main characteristics of the model and to discuss it.},
	keywords = {application, architecture, autonomic, goal, hardware, model, reconfigurable, run-time environment, self-adaptivity, software},
	issn = {1383-7621},
	doi = {http://dx.doi.org/10.1016/j.sysarc.2008.07.002},
	author = {Derin, Onur and Ferrante, Alberto and Taddeo, Antonio Vincenzo}
}
@conference {106.BoSa09,
	title = {Creating an Embedded Systems Program from Scratch: Nine years of experience at ALaRI},
	booktitle = {Proceedings of the 2009 Workshop on Embedded System Education},
	year = {2009},
	month = {October},
	address = {Grenoble, France},
	abstract = {In 1999, experts form academia and industry met in a workshop dealing with education in Embedded Systems Design: at the time there were no specifically oriented programs, and an {\textquoteright}ideal{\textquoteright} educational track was designed. One year later, that educational design was implemented with a one-year {\textquoteright}executive-type{\textquoteright} Master at Universit{\`a} della Svizzera italiana, in Switzerland; over the years, the program blossomed and extended, with development of a two-year Master of Science program as well. The experience is discussed here; results and perspectives are analyzed.},
	keywords = {education, embedded systems},
	doi = {http://dx.doi.org/10.1145/1719010.1719012},
	author = {Bondi, Umberto and Sami, Mariagiovanna}
}
@conference {89.ReEiBrIeKo,
	title = {Can knowledge regarding the presence of countermeasures against fault attacks simplify power attacks on cryptographic devices?},
	booktitle = {Proceedings of 23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS 08)},
	year = {2008},
	month = {October 1-3},
	abstract = {Side-channel attacks are nowadays a serious concern when implementing cryptographic algorithms. Powerful ways for gaining information about the secret key as well as various countermeasures against such attacks have been recently developed. Although it is well known that such attacks can exploit information leaked from different sources, most prior works have only addressed the problem of protecting a cryptographic device against a single type of attack. Consequently, there is very little knowledge on how a scheme for protecting a device against one type of side-channel attack may affect its vulnerability to other types of side-channel attacks. In this paper we focus on devices that include protection against fault injection attacks (using different error detection schemes) and explore whether the presence of such fault detection circuits affects the resistance against attacks based on power analysis. Using the AES S-Box as an example, we performed attacks on the unprotected implementation as well as modified implementations with parity check circuits or residue check circuits (mod3 and mod7). In particular, we focus on the question whether the knowledge of the presence of error detection circuitry in the cryptographic device can help an attacker who attempts to mount a power attack on the device. Our results show that the presence of error detection circuitry helps the attacker even if he is unaware of this circuitry, and that the benefit to the attacker increases with the number of check bits used for the purpose of error detection.},
	author = {Regazzoni, Francesco and Eisenbarth, Thomas and Breveglieri, Luca and Ienne, Paolo and Koren, Israel}
}
@conference {85.MuSaParma08,
	title = {Code Generation from Statecharts: Simulation of Wireless Sensor Networks},
	booktitle = {Proceedings of DSD08},
	year = {2008},
	month = {September},
	address = {Parma, Italy},
	abstract = {Automatic generation of code starting from lightweight modeling languages such as UML is by now a widely adopted approach. In particular generation of executable SystemC models starting from StateCharts and other UML diagrams represents a promising research field. While RTL SystemC appears better suited for matching the StateCharts formalism (being intrinsically clocked), performances of the generated code suffer from the heavy overhead induced by time management, specially when the number of concurrent processes is high. In this paper we present a methodology that allows applying a solution mixing event based and clock-driven approach. More specifically, clock-driven simulation is activated only when the configuration of the system is identified to be evolving. When no events are present this fact is also detected (together with the interval of absence of events) so that no simulation is performed although the clock runs on. This solution is particularly suited for low duty cycle systems, as, e.g. when simulating Wireless Sensor Networks (WSN); in such instances, speedup of the generated code has been found to be well over two orders of magnitude. Application of the technique to the generation of a power simulator for the IEEE 802.15.4 networking protocol is used as a test case.},
	keywords = {low power design, modeling, protocol, wireless sensor networks},
	doi = {http://dx.doi.org/10.1109/DSD.2008.106},
	author = {Mura, Marcello and Sami, Mariagiovanna}
}
@conference {45.BoTa2006,
	title = {COOPER: Towards A Collaborative Open Environment of Project-centred Learning},
	booktitle = {proceedings to EC-TEL{\textquoteright}06 conference},
	year = {2006},
	month = {October 1-4},
	address = {Crete, Greece},
	abstract = {Nowadays, engineering studies are characterized by high mobility of students, lecturers and workforce and by the dynamics of multi-national companies where classes or students{\textquoteright} teams composed of persons with different competencies and backgrounds, working together in projects to solve complex problems. Such an environment will become increasingly relevant in multinational universities and companies, and it has brought a number of challenges to existing e-learning technologies. COOPER is an ongoing project that focuses on developing and testing such a collaborative and project-centred leaning environment. This paper proposes a COOPER framework and shows its approaches to address the various research challenges.},
	keywords = {project-centred learning, remote cooperation},
	author = {Bongio, Aldo and Bruggen, Jan and Ceri, Stefano and Cristea, Valentin and Dolog, Peter and Hoffmann, Andreas and Matera, Maristella and Mura, Marzia and Taddeo, Antonio Vincenzo and Zhou, Xuan and Zoni, Larissa}
}
