@conference {75.BoPaSa08,
	title = {An adaptable FPGA-based System for Regular Expression Matching},
	booktitle = {Proceedings of Design, Automation and Test in Europe (DATE) Conference},
	year = {2008},
	month = {March 10-14},
	address = {Munich, Germany},
	abstract = {In many applications string pattern matching is one of the most intensive tasks in terms of computation time and memory accesses. Network Intrusion Detection Systems and DNA Sequence Matching are two examples. Since software solutions are not able to satisfy the performance requirements, specialized hardware architectures are required. In this paper we propose a complete framework for regular expression matching, both in its architecture and compiler. This special-purpose processor is programmed using regular expressions as programming language. With the parallelism exploited in the design it is possible to achieve a throughput greater than one character per clock cycle, requiring O(n) memory space. The VHDL description of the proposed architecture is fully configurable. A design space exploration to find the optimal architecture based on area and performance cost-function is presented.},
	keywords = {FPGA-based design, regular expression matching},
	doi = {http://dx.doi.org/10.1109/DATE.2008.4484852},
	author = {Bonesana, Ivano and Paolieri, Marco and Santambrogio, Marco Domenico}
}
@conference {49.MuPaNeSaFa07,
	title = {Power Modeling and Power Analysis for IEEE 802.15.4: a Concurrent State Machine Approach},
	booktitle = {Proceedings of CCNC 2007},
	year = {2007},
	month = {January 11-13},
	address = {Las Vegas, USA},
	abstract = {802.15.4 is a recent low-rate/low-power standard for wireless personal area and sensor networks. Its simple infrastructure, intermediate range and good power performance make it a candidate for applications that require a reasonably low throughput but a very high device lifetime and power efficiency. An experimental power analysis of an 802.15.4 implementation is carried out, providing a detailed power model of the protocol based on concurrent state machines; resulting power model is then used to generate a customized simulator. The model has been validated through a set of experiments and provides good accuracy; results are discussed, considering in particular use of the model as a basis for subsequent optimizations on 802.15.4 networks.},
	keywords = {low power design, modeling, wireless sensor networks},
	doi = {http://dx.doi.org/10.1109/CCNC.2007.135},
	author = {Mura, Marcello and Paolieri, Marco and Negri, Luca and Fabbri, Fabio and Sami, Mariagiovanna}
}
@conference {70.PaBoSa07,
	title = {ReCPU: a Parallel and Pipelined Architecture for Regular Expression Matching},
	booktitle = {Proceedings of 15th Annual IFIP International Conference on Very Large Scale Integration {(IFIP-VLSI 07)},(best paper award)},
	year = {2007},
	month = {October 15-17},
	address = {Atlanta, Georgia, USA},
	abstract = {Text pattern matching is one of the main and most computation intensive parts of systems such as Network Intrusion Detection Systems and DNA Sequencing Matching. Soft- ware solutions to this are available but often they do not satisfy the requirements in terms of performance. This pa- per presents a new hardware approach for regular expression matching: ReCPU. The proposed solution is a parallel and pipelined architecture able to deal with the common regular expression semantics. This implementation based on several parallel units achieves a throughput of more than one char- acter per clock cycle (maximum performance of state of the art solutions) requiring just O(n) memory locations (where n is the length of the regular expression). Performance has been evaluated synthesizing the VHDL description. Area and time constraints have been analyzed. Experimental re- sults are obtained simulating the architecture.},
	doi = {http://dx.doi.org/10.1109/VLSISOC.2007.4402466},
	author = {Paolieri, Marco and Bonesana, Ivano and Santambrogio, Marco Domenico}
}
@conference {64.Barcellona2,
	title = {SC2: State Charts to System C: Automatic Executable Models Generation},
	booktitle = {proceedings FDL07},
	year = {2007},
	month = {September},
	address = {Barcelona, Spain},
	abstract = {The recent development of embedded systems calls for the necessity of a complete framework for design and simulation of applications that span through all levels of system design. Desirable characteristics of such a framework are rapidity of use, simplicity and reusability. For this purpose we already introduced a generator that converts specifications written with a subset of StateCharts to behavioral SystemC [9] [11]. In this paper we present the new version of our tool: most of the limitations of the previous versions have been overcome, the considered subset of the StateCharts formalism has been extended and the target has been changed from behavioral to Register Tranfer Level (RTL) SystemC. A major enhancement of this new version is the possibility of obtaining various module instances starting from a single specification, which is vital in some contexts (e.g. Wireless Sensors Networks simulation). The semantics chosen for our StateCharts diagrams is clearly described. The generation of executable models as well as the kernel template of the generated code are discussed in detail.},
	keywords = {code generation, StateCharts, SystemC, unified modeling language (UML)},
	author = {Mura, Marcello and Paolieri, Marco}
}
@conference {50.MuPaNeSa07,
	title = {StateCharts to SystemC: a High Level Hardware Simulation Approach},
	booktitle = {Proceedings of GLSVLSI 2007},
	year = {2007},
	month = {March 11-13},
	address = {Stresa, Italy},
	abstract = {In this paper we present a tool that converts specifications written with a subset of StateCharts into SystemC behavioral models. The main advantages of such an approachare rapidity of use, simplicity and reusability. Various systems can be modeled at different levels of abstraction and accuracy through StateCharts and different peculiar aspects (e.g. energy, performances) can be taken into consideration. Moreover different parts of the design can be identified at different detail levels. The kernel of the simulator is fully discussed together with its mapping to the semantics of our StateCharts diagrams. As a case study we present here a model of the IBM PowerPC 750 Cache system and the respective SystemC simulator automatically generated by our tool.},
	keywords = {code generation, StateCharts, SystemC, unified modeling language (UML)},
	doi = {http://dx.doi.org/10.1145/1228784.1228904},
	author = {Mura, Marcello and Paolieri, Marco and Negri, Luca and Sami, Mariagiovanna}
}
