@conference {18477,
	title = {Challenges in designing trustworthy cryptographic co-processors},
	booktitle = {IEEE International Symposium on Circuits and Systems (ISCAS) 2015},
	year = {2015},
	month = {09/2015},
	pages = {2009-2012},
	publisher = {IEEE},
	organization = {IEEE},
	address = {Lisbon, Portugal},
	abstract = {Security is becoming ubiquitous in our society. However, the vulnerability of electronic devices that implement the needed cryptographic primitives has become a major issue. This paper starts by presenting a comprehensive overview of the existing attacks to cryptography implementations. Thereafter, the state-of-the-art on some of the most critical aspects of designing cryptographic co-processors are presented. This analysis starts by considering the design of asymmetrical and symmetrical cryptographic primitives, followed by the discussion on the design and online testing of True Random Number Generation. To conclude, techniques for the detection of Hardware Trojans are also discussed},
	keywords = {asymmetrical cryptographic primitives, cryptography, hardware Trojan detection techniques},
	issn = {0271-4302 },
	doi = {10.1109/ISCAS.2015.7169070},
	url = {http://dx.doi.org/10.1109/ISCAS.2015.7169070},
	author = {Regazzoni, Francesco and Graves, Ricardo and Di Natale, Giorgio and Batina, Lejla and Bhasin, Shivam and Ege, Baris and Fournaris, Apostolos P. and Mentens, Nele and Picek, Stjepan and Rozic, Vladimir and Sklavos, Nicolas and Yang, Bohan}
}
@inbook {18092,
	title = {Design Space Exploration for Run-Time Management of a Reconfigurable System for Video Streaming},
	booktitle = {Multi-objective design space exploration of multiprocessor SoC architectures: the MULTICUBE approach},
	year = {2011},
	pages = {189-204},
	publisher = {Springer},
	organization = {Springer},
	edition = {1},
	isbn = {978-1-4419-8836-2},
	author = {Mariani, Giovanni and Avasare, Prabhat and Ykman-Couvreur, Chantal and Vanmeerbeeck, Geert and Palermo, Gianluca and Silvano, Cristina and Zaccaria, Vittorio},
	editor = {Silvano, Cristina and Fornaciari, William and Villar, Eugenio}
}
@inbook {138.MaAvYkVaPaSiZa.2011,
	title = {Design Space Exploration of a Reconfigurable System for Supporting Video Streaming Run-time Management},
	booktitle = {Multi-objective design space exploration of multiprocessor SoC architectures: the MULTICUBE approach},
	year = {2011},
	publisher = {Springer},
	organization = {Springer},
	address = {New York, USA},
	abstract = {This paper reports a case study of Design Space Exploration for supporting Run-time Resource Management (RRM). In particular the management of system resources for an MPSoC dedicated to multiple MPEG4 encoding is addressed in the context of an Automotive Cognitive Safety System (ACSS). The runtime management problem is defined as the minimization of the platform power consumption under resource and Quality of Service (QoS) constraints. The paper provides an insight of both, design-time and run-time aspects of the problem. During the prelimiary design-time Design Space Exploration (DSE) phase, the best configurations of run-time tunable parameters are statically identified for providing the best trade-offs in terms of run-time costs and application QoS. To speed up the optimization process without reducing the quality of final results, a multi-simulator framework is used for modeling platform performance. At run-time, the RRM exploits the design-time DSE results for deciding an operating configuration to be loaded for each MPEG4 encoder. This operation is carried out dynamically, by following the QoS requirements of the specific use-case.},
	author = {Mariani, Giovanni and Avasare, Prabhat and Ykman-Couvreur, Chantal and Vanmeerbeeck, Geert and Palermo, Gianluca and Silvano, Cristina and Zaccaria, Vittorio}
}
@inbook {144.AvYkVaMaPaSiZa.2011,
	title = {Design Space Exploration Supporting Run-time Resource Management},
	booktitle = {Multi-objective design space exploration of multiprocessor SoC architectures: the MULTICUBE approach},
	year = {2011},
	publisher = {Springer},
	organization = {Springer},
	address = {New York, USA},
	abstract = {Running multiple applications optimally in terms of Quality of Service (e.g., performance and power consumption) on embedded multi-core platforms is a huge challenge.Moreover, current applications exhibit unpredictable changes of the environment and workload conditions which makes the task of running them optimally even more difficult. This dynamic trend in application runs will grow even more in future applications. This paper presents an automated tool flow which tackles this challenge by a two-step approach: first at design-time, a Design Space Exploration (DSE) tool is coupled with a platform simulator(s) to get optimum operating points for the set of target applications. Secondly, at run-time, a lightweight Run-time Resource Manager (RRM) leverages the design-time DSE results for deciding an operating configuration to be loaded at run-time for each application. This decision is performed dynamically, by taking into consideration available platform resources and the QoS requirements of the specific use-case. To keep RRM execution and resource overhead at minimum, a very fast optimisation heuristic is integrated. Application of this tool-flow on a real-life multimedia use case (described in Chapter 9 of the book of this paper) will demonstrate a significant speedup in optimisation process while maintaining desired Quality of Service.},
	author = {Avasare, Prabhat and Ykman-Couvreur, Chantal and Vanmeerbeeck, Geert and Mariani, Giovanni and Palermo, Gianluca and Silvano, Cristina and Zaccaria, Vittorio}
}
@conference {18086,
	title = {FPGA Implementations of the AES Masked Against Power Analysis Attacks},
	booktitle = {2nd International Workshop on Constructive Side-Channel Analysis and Secure Design (COSADE)},
	year = {2011},
	month = {February},
	address = {Darmstadt, Germany},
	author = {Regazzoni, Francesco and Yi, Wang and Standaert, Fran{\c c}ois-Xavier}
}
@article {145.YkAvMaZaPaSi11,
	title = {Linking run-time resource management of embedded multi-core platforms with automated design-time exploration},
	journal = {IET Computers and Digital Techniques},
	volume = {5},
	number = {-},
	year = {2011},
	pages = {123{\textendash}135},
	abstract = {Nowadays, owing to unpredictable changes of the environment and workload variation, optimally running multiple applications in terms of quality, performance and power consumption on embedded multi-core platforms is a huge challenge. A lightweight run-time manager, linked with an automated design-time exploration and incorporated in the host processor of the platform, is required to dynamically and efficiently configure the applications according to the available platform resources (e.g. processing elements, memories, communication bandwidth), for minimising the cost (e.g. power consumption), while satisfying the constraints (e.g. deadlines). This study presents a flow linking a design-time design space explorer, coupled with platform simulators at two abstraction levels, with a fast and lightweight priority-based heuristic integrated in the run-time manager to select near-optimal application configurations. To illustrate its feasibility and the very low complexity of the run-time selection, the proposed flow is used to manage the processors and clock frequencies of a multiple-stream MPEG4 encoder chip dedicated to automotive cognitive safety applications.},
	doi = {http://dx.doi.org/10.1049/iet-cdt.2010.0030},
	author = {Ykman-Couvreur, Chantal and Avasare, Prabhat and Mariani, Giovanni and Zaccaria, Vittorio and Palermo, Gianluca and Silvano, Cristina}
}
@inbook {17734,
	title = {The MULTICUBE Design Flow},
	booktitle = {Multi-objective Design Space Exploration of Multiprocessor SoC Architectures},
	year = {2011},
	pages = {3-17},
	publisher = {Springer New York},
	organization = {Springer New York},
	isbn = {978-1-4419-8836-2},
	doi = {10.1007/978-1-4419-8837-9_1},
	url = {http://dx.doi.org/10.1007/978-1-4419-8837-9_1},
	author = {Silvano, Cristina and Fornaciari, William and Palermo, Gianluca and Zaccaria, Vittorio and Castro, Fabrizio and Martinez, Marcos and Bocchio, Sara and Zafalon, Roberto and Avasare, Prabhat and Vanmeerbeeck, Geert and Ykman-Couvreur, Chantal and Wouters, Maryse and Kavka, Carlos and Onesti, Luka and Turco, Alessandro and Bondi, Umberto and Mariani, Giovanni and Posadas, Hector and Villar, Eugenio and Wu, Chris and Dongrui, Fan and Hao, Zhang},
	editor = {Silvano, Cristina and Fornaciari, William and Villar, Eugenio}
}
@inbook {139.Sietal2.2011,
	title = {MULTICUBE: Multi-Objective Design Space Exploration of Multi-Core Architectures},
	booktitle = {VLSI 2010 Annual Symposium},
	volume = {105},
	year = {2011},
	pages = {47-63},
	publisher = {Springer},
	organization = {Springer},
	address = {Netherlands},
	abstract = {Given the increasing complexity of Chip Multi-Processors (CMPs), a wide range of architecture parameters must be explored at design time to find the best trade-off in terms of multiple competing objectives (such as energy, delay, bandwidth, area, etc.) The design space of the target architectures is huge because it should consider all possible combinations of each hardware parameter (e.g., number of processors, processor issue width, L1 and L2 cache sizes, etc.). In this complex scenario, intuition and past experience of design architects is no more a sufficient condition to converge to an optimal design of the system. Indeed, Automatic Design Space Exploration (DSE) is needed to systematically support the analysis and quantitative comparison of a large amount of design alternatives in terms of multiple competing objectives (by means of Pareto analysis). The main goal of the MULTICUBE project consists of the definition of an automatic Design Space Exploration framework to support the design of next generation many-core architectures.},
	isbn = {978-94-007-1487-8},
	url = {http://dx.doi.org/10.1007/978-94-007-1488-5_4},
	author = {Silvano, Cristina and Fornaciari, William and Palermo, Gianluca and Zaccaria, Vittorio and Castro, Fabrizio and Martinez, Marcos and Bocchio, Sara and Zafalon, Roberto and Avasare, Prabhat and Vanmeerbeeck, Geert and Ykman-Couvreur, Chantal and Wouters, Maryse and Kavka, Carlos and Onesti, Luka and Turco, Alessandro and Bondi, Umberto and Mariani, Giovanni and Posadas, Hector and Villar, Eugenio and Wu, Chris and Dongrui, Fan and Hao, Zhang and Shibin, Tang}
}
@conference {114.MaYkZhZhLa10,
	title = {An Efficient Run-Time Management Methodology for Stereo Matching Application},
	booktitle = {2PARMA: Proceedings of the Workshop on Parallel Programming and Run-time Management Techniques for Many-core Architectures},
	year = {2010},
	month = {February},
	address = {Hannover, Germany},
	abstract = {This paper presents a methodology for Run-Time Management (RTM) of algorithmic parameters. The RTM is able to trade-off the algorithm output quality and the execution time. Thus, once a requirement in terms of maximum execution time is set, the RTM dynamically tunes the parameters in order to maximize the output quality while respecting the given requirement. The run-time decision making relies on design-time modeling techniques able to characterize key relations between algorithm parameters, execution time and output quality. Models generated during the design-time analysis are accurate enough to drive the RTM in its decision making while enough generic to model application behaviors over datasets which were not included at design-time. In this paper the methodology is applied on the Stereo Matching application, a computational intensive artificial vision application aimed at inferring object depths using two or more cameras. Experimental results prove the effectiveness of the methodology which is able to identify high quality solutions respecting required deadline while introducing negligible overhead.},
	author = {Mariani, Giovanni and Ykman-Couvreur, Chantal and Zhang, Ke and Zhang, Lu and Lafruit, Gauthier}
}
@conference {117.MaAvVaYkPaSiZa10,
	title = {An industrial design space exploration framework for supporting run-time resource management on multi-core systems},
	booktitle = {Proceedings of Design, Automation and Test in Europe (DATE) Conference},
	year = {2010},
	month = {March},
	address = {Dresden, Germany},
	abstract = {Current multi-core design methodologies are facing increasing unpredictability in terms of quality due to the actual diversity of the workloads that characterize the deployment scenario. To this end, these systems expose a set of dynamic parameters which can be tuned at run-time to achieve a specified Quality of Service (QoS) in terms of performance. A run-time manager operating system module is in charge of matching the specified QoS with the available platform resources by manipulating the overall degree of task-level parallelism of each application as well as the frequency of operation of each of the system cores. In this paper, we introduce a design space exploration framework for enabling and supporting enhanced resource management through software re-configuration on an industrial multicore platform. From one side, the framework operates at design time to identify a set of promising operating points which represent the optimal trade-off in terms of the target power consumption and performance. The operating points are used after the system has been deployed to support an enhanced resource management policy. This is done by a light-weight resource management layer which filters and selects the optimal parallelism of each application and operating frequency of each core to achieve the QoS constraints imposed by the external world and/or the user. We show how the proposed design-time and run-time techniques can be used to optimally manage the resources of a multiple-stream MPEG4 encoding chip dedicated to automotive cognitive safety tasks.},
	author = {Mariani, Giovanni and Avasare, Prabhat and Vanmeerbeeck, Geert and Ykman-Couvreur, Chantal and Palermo, Gianluca and Silvano, Cristina and Zaccaria, Vittorio}
}
@conference {119.AvVaYkMaPaZaSi10,
	title = {Linking run-time management with design space exploration at multiple abstraction levels},
	booktitle = {Proceedings of the DATE{\textquoteright}10 workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications},
	year = {2010},
	month = {March},
	address = {Dresden, Germany},
	abstract = {In present era of Multi-Processor System-on-Chip (MPSoC) embedded devices, to run multiple applications optimally (in terms of execution time and power consumption) is an enormous challenge. Embedded designers usually tackle this challenge by dividing it in two parts : at design-time Design Space Explorations (DSE) are performed to derive Pareto set of optimum operating points for each application and at run-time embedded device is monitored continuously to operate at one of the points in the derived Pareto set. Obviously run-time management relies heavily on accuracy of DSE. With growing complexity of embedded devices and with time-to-market pressures, at design-time, it is not trivial to derive the operating point Pareto set. On the other hand, at run-time, overhead introduced by a run-time management scheme should also not be high so as to minimally affect embedded device performance . We have developed techniques to tackle these embedded design issues. At design time, we use DSE with multiple simulators running at multiple abstraction levels to converge quickly to Pareto set of operating points. At runtime, to keep run-time overhead to a minimum, a hierarchical Runtime Resource Manager (RRM) is used with well-defined interfaces (services) between global and local resource managers. We applied our methodology on an embedded device having eight processor cores running multiple MPEG4 encoders. With our DSE methodology, we could derive Pareto set much quickly (as compared to full-space explorations). With our run-time schemes, overhead introduced by run-time manager was negligible.},
	author = {Avasare, Prabhat and Vanmeerbeeck, Geert and Ykman-Couvreur, Chantal and Mariani, Giovanni and Palermo, Gianluca and Zaccaria, Vittorio and Silvano, Cristina}
}
@conference {129.Sietal.ISVLSI11,
	title = {Multicube: Multi-objective design space exploration of multi-core architectures},
	booktitle = {ISVLSI 2010: IEEE Annual Symposium on VLSI},
	year = {2010},
	month = {July},
	pages = {488{\textendash}493},
	address = {Lixouri, Kefalonia - Greece},
	abstract = {Technology trends enable the integration of many processor cores in a System-on-Chip (SoC). In these complex architectures, several architectural parameters can be tuned to find the best trade-off in terms of multiple metrics such as energy and delay. The main goal of the MULTICUBE project consists of the definition of an automatic Design Space Exploration framework to support the design of next generation many-core architectures.},
	doi = {http://dx.doi.org/10.1109/ISVLSI.2010.67},
	author = {Silvano, Cristina and Fornaciari, William and Palermo, Gianluca and Zaccaria, Vittorio and Castro, Fabrizio and Martinez, Marcos and Bocchio, Sara and Zafalon, Roberto and Avasare, Prabhat and Vanmeerbeeck, Geert and Ykman-Couvreur, Chantal and Wouters, Maryse and Kavka, Carlos and Onesti, Luka and Turco, Alessandro and Bondi, Umberto and Mariani, Giovanni and Posadas, Hector and Villar, Eugenio and Wu, Chris and Dongrui, Fan and Hao, Zhang and Shibin, Tang}
}
