@article {18547,
	title = {Anomaly and Change Detection in Graph Streams through Constant-Curvature Manifold Embeddings},
	journal = {IJCNN 2018 : International Joint Conference on Neural Networks},
	year = {2018},
	month = {07/2018},
	author = {Zambon, Daniele and Livi, Lorenzo and Alippi, Cesare}
}
@conference {18592,
	title = {Arbon Demonstrator Eye-on-the-Grid, from Concept to Results},
	booktitle = {SCCER-FURIES Annual Conference},
	year = {2018},
	month = {12/2018},
	url = {https://sccer-furies.epfl.ch/wp-content/uploads/2019/01/Arbon-demo-FURIES-Annual-meeting.pdf},
	author = {Lukovi{\'c}, Slobodan and Gasparin, Alberto and Witzig, Jens and Herbst, Ingo}
}
@conference {18593,
	title = {A characterization of the Edge of Criticality in Binary Echo State Networks},
	booktitle = {2018 IEEE 28th International Workshop on Machine Learning for Signal Processing (MLSP)},
	year = {2018},
	month = {09/2018},
	address = {Aalborg, Denmark},
	author = {Verzelli, Pietro and Livi, Lorenzo and Alippi, Cesare}
}
@article {18545,
	title = {Concept Drift and Anomaly Detection in Graph Streams},
	journal = {IEEE Transactions on Neural Networks and Learning Systems},
	volume = {29},
	issue = {11},
	year = {2018},
	month = {11/2018},
	pages = {5592-5605},
	chapter = {5592},
	author = {Zambon, Daniele and Alippi, Cesare and Livi, Lorenzo}
}
@article {18533,
	title = {Determination of the Edge of Criticality in Echo State Networks Through Fisher Information Maximization},
	journal = {IEEE Transactions on Neural Networks and Learning Systems},
	volume = {29},
	year = {2018},
	month = {March},
	pages = {706-717},
	keywords = {Echo state network (ESN), echo state networks, edge of criticality, ESN, Fisher information, Fisher information matrix, Fisher information maximization, Jacobian matrices, Learning systems, Neurons, nonparametric estimation, nonparametric estimator, nonparametric statistics, prediction error, Probability density function, recurrent neural nets, recurrent neural networks, Reservoirs, RNN, short-term memory capacity, Training},
	issn = {2162-237X},
	doi = {10.1109/TNNLS.2016.2644268},
	author = {Livi, Lorenzo and Bianchi, Filippo Maria and Alippi, Cesare}
}
@inbook {18529,
	title = {Extinguishing Ransomware - A Hybrid Approach to Android Ransomware Detection},
	booktitle = {Foundations and Practice of Security},
	volume = {10723},
	year = {2018},
	month = {02/2018},
	pages = {242-258},
	publisher = {Springer International Publishing},
	organization = {Springer International Publishing},
	address = {Cham},
	abstract = {Mobile ransomware is on the rise and effective defense from it is of utmost importance to guarantee security of mobile users{\textquoteright} data. Current solutions provided by antimalware vendors are signature-based and thus ineffective in removing ransomware and restoring the infected devices and files. Also, current state-of-the art literature offers very few solutions to effectively detecting and blocking mobile ransomware. Starting from these considerations, we propose a hybrid method able to effectively counter ransomware. The proposed method first examines applications to be used on a device prior to their installation (static approach) and then observes their behavior at runtime and identifies if the system is under attack (dynamic approach). To detect ransomware, the static detection method uses the frequency of opcodes while the dynamic detection method considers CPU usage, memory usage, network usage and system call statistics. We evaluate the performance of our hybrid detection method on a dataset that contains both ransomware and legitimate applications. Additionally, we evaluate the performance of the static and dynamic stand-alone methods for comparison. Our results show that although both static and dynamic detection methods perform well in detecting ransomware, their combination in a form of a hybrid method performs best, being able to detect ransomware with 100{\%} precision and having a false positive rate of less than 4{\%}.},
	isbn = {978-3-319-75650-9},
	doi = {https://doi.org/10.1007/978-3-319-75650-9_16},
	author = {Ferrante, Alberto and Malek, Miroslaw and Martinelli, Fabio and Mercaldo, Francesco and Milosevic, Jelena},
	editor = {Imine, Abdessamad and Fernandez, Jos{\'e} M. and Marion, Jean-Yves and Logrippo, Luigi and Garcia-Alfaro, Joaquin}
}
@article {18508,
	title = {Investigating echo state networks dynamics by means of recurrence analysis},
	journal = {IEEE Transactions on Neural Networks and Learning Systems},
	volume = {29},
	year = {2018},
	month = {02/2018},
	pages = { 427 - 439},
	abstract = {In this paper, we elaborate over the well-known
interpretability issue in echo state networks. The idea is to investigate
the dynamics of reservoir neurons with time-series analysis
techniques taken from research on complex systems. Notably, we
analyze time-series of neuron activations with Recurrence Plots
(RPs) and Recurrence Quantification Analysis (RQA), which
permit to visualize and characterize high-dimensional dynamical
systems. We show that this approach is useful in a number of
ways. First, the two-dimensional representation offered by RPs
provides a way for visualizing the high-dimensional dynamics of
a reservoir. Our results suggest that, if the network is stable,
reservoir and input denote similar line patterns in the respective
RPs. Conversely, the more unstable the ESN, the more the RP
of the reservoir presents instability patterns. As a second result,
we show that the Lmax measure is highly correlated with the
well-established maximal local Lyapunov exponent. This suggests
that complexity measures based on RP diagonal lines distribution
provide a valuable tool to quantify the degree of network stability.
Finally, our analysis shows that all RQA measures fluctuate on
the proximity of the so-called edge of stability, where an ESN
typically achieves maximum computational capability. We verify
that the determination of the edge of stability provided by such
RQA measures is more accurate than two well-known criteria
based on the Jacobian matrix of the reservoir. Therefore, we
claim that RPs and RQA-based analyses can be used as valuable
tools to design an effective network given a specific problem.},
	doi = {10.1109/TNNLS.2016.2630802},
	author = {Bianchi, Filippo Maria and Livi, Lorenzo and Alippi, Cesare}
}
@conference {18530,
	title = {Time series kernel similarities for predicting Paroxysmal Atrial Fibrillation from ECGs},
	booktitle = { IJCNN 2018 : International Joint Conference on Neural Networks},
	year = {2018},
	month = {07/2018},
	publisher = {IEEE},
	organization = {IEEE},
	address = {Rio, Brazil},
	author = {Bianchi, Filippo Maria and Livi, Lorenzo and Ferrante, Alberto and Milosevic, Jelena and Malek, Miroslaw}
}
@conference {18538,
	title = {Critical echo state network dynamics by means of Fisher information maximization},
	booktitle = {2017 International Joint Conference on Neural Networks (IJCNN)},
	year = {2017},
	month = {May},
	keywords = {Asymptotic stability, critical phase transitions, echo state network, edge of criticality, Electronic mail, ESN, Estimation, estimation theory, FIM, Fisher information matrix, Fisher information maximization, hidden neurons activations, high short term memory capacity, input signal, low prediction error, network dynamics, network theory (graphs), Neurons, optimisation, Probability density function, recurrent neural nets, Reservoirs, signal processing, statistics, Tuning, unsupervised approach, unsupervised learning},
	doi = {10.1109/IJCNN.2017.7965941},
	author = {Bianchi, Filippo Maria and Livi, Lorenzo and Jenssen, Robert and Alippi, Cesare}
}
@conference {18542,
	title = {Detecting changes in sequences of attributed graphs},
	booktitle = {2017 IEEE Symposium Series on Computational Intelligence (SSCI)},
	year = {2017},
	month = {Nov},
	keywords = {Aerospace electronics, Anomaly detection, application domains, Attributed graph, attributed graphs, Change detection, Concept drift, Dynamic/Evolving graph, Electronic mail, Embedding, geometric graphs, Graph matching, graph theory, graph-based representations, Markov chains, Markov processes, Microsoft Windows, pair-wise relations, Prototypes, real-world systems, Stationarity, topology, Training, variable order},
	doi = {10.1109/SSCI.2017.8285273},
	author = {Zambon, Daniele and Livi, Lorenzo and Alippi, Cesare}
}
@conference {18537,
	title = {A lightweight and energy-efficient Internet-of-birds tracking system},
	booktitle = {2017 IEEE International Conference on Pervasive Computing and Communications (PerCom)},
	year = {2017},
	month = {March},
	keywords = {animal movement tracking, application server, Birds, cellular radio, cloud computing, energy assessment, energy conservation, energy consumption, energy efficient Internet-of-birds tracking system, GSM, GSM-based tracking device energy consumption reduction, Internet of Things, Internet-of-things vision, joint localization-transmission phase, Northern Italy, quality of service, Radar tracking, Receivers, Satellites, telecommunication power management, Tracking, Transmitters},
	doi = {10.1109/PERCOM.2017.7917862},
	author = {Alippi, Cesare and Ambrosini, Roberto and Longoni, Violetta and Cogliati, Dario and Roveri, Manuel}
}
@article {18532,
	title = {Multiplex visibility graphs to investigate recurrent neural network dynamics},
	journal = {Nature-Scientific reports},
	volume = {7},
	year = {2017},
	month = {03/2017},
	pages = {44037-44049},
	chapter = {44037},
	doi = {doi:10.1038/srep44037},
	author = {Bianchi, Filippo Maria and Livi, Lorenzo and Alippi, Cesare and Jenssen, Robert}
}
@article {18510,
	title = {One-class classifiers based on entropic spanning graphs},
	journal = {IEEE Transactions on Neural Networks and Learning Systems},
	volume = {28},
	issue = {12},
	year = {2017},
	month = {11/2016},
	pages = { 2846 - 2858},
	chapter = {2846},
	abstract = {One-class classifiers offer valuable tools to assess the presence of outliers in data. In this paper, we propose a design methodology for one-class classifiers based on entropic spanning graphs. The spanning graph is learned on the embedded input data, with the aim to generate a partition of the vertices.
The final partition is derived by exploiting a criterion based on mutual information minimization. Here, we compute the mutual information by using a convenient formulation provided in terms of the alfa-Jensen difference. Once training is completed, in order to associate a confidence level with the classifier decision, a graph-based fuzzy model is constructed. The fuzzification process is based only on topological information of the vertices of the entropic spanning graph. As such, the proposed one-class classifier is suitable also for datasets with complex geometric structures. We provide experiments on well-known benchmarking datasets containing both feature vectors and labeled graphs. In addition, we apply the method on the problem of protein solubility recognition by considering several data representations for the samples. Experimental results demonstrate the effectiveness and versatility of the proposed method with respect to other state-of the-art approaches.
},
	doi = { 10.1109/TNNLS.2016.2608983},
	author = {Livi, Lorenzo and Alippi, Cesare}
}
@article {18455,
	title = {A Framework for Disturbance Analysis in Smart Grids by Fault Injection},
	journal = {Springer Journal on "Computer Science - Research and Development"},
	year = {2016},
	month = {09/2016},
	abstract = {With growing complexity of electric power systems, a total number of disturbances is expected to increase. Analyzing these disturbances and understanding grid{\textquoteright}s behavior, when under a disturbance, is a pre-requisite for designing methods for boosting grid{\textquoteright}s stability. The main obstacle to the analysis is a lack of relevant data that are publicly available. In this paper, we design and implement a framework for emulation of grid disturbances by employing simula-tion and fault-injection techniques. We also present a case study on generating voltage sag related data. A foreseen usage of the framework considers mainly prototyping, root-cause analysis and design and comparison of methods for disturbance detection and prediction. },
	issn = {1865-2042},
	doi = {10.1007/s00450-016-0313-8},
	url = {http://dx.doi.org/10.1007/s00450-016-0313-8},
	author = {Kaitovi{\'c}, Igor and Obradovi{\'c}, Filip and Lukovi{\'c}, Slobodan and Malek, Miroslaw}
}
@conference {18503,
	title = {A Methodology for Proactive Maintenance of Uninterruptible Power Supplies},
	booktitle = {Latin-American Symposium on Dependable Computing  (LADC2016) - Workshop on Dependability in Evolving Systems (WDES)},
	year = {2016},
	month = {10/2016},
	address = {Cali, Colombia},
	abstract = {We propose a methodology for proactive maintenance of Uninterruptible Power Supply (UPS) devices based on online health-status monitoring and application of data analytics for prediction of UPS components{\textquoteright} failures. The goals of the work are (i) improvement of reliability of UPS devices by ensuring prompt action prior to a failure of a component, and (ii) provision of more cost-effective maintenance by servicing the device only when required instead of periodically. Improving reliability of UPS{\textquoteright}es also enhances dependability of critical infrastructures that require high quality power supply.},
	author = {Lukovi{\'c}, Slobodan and Kaitovi{\'c}, Igor and Lecuona, Gerardo and Malek, Miroslaw}
}
@conference {18448,
	title = {One-Class Classification Through Mutual Information Minimization},
	booktitle = {IEEE-INNS  International Joint Conference on Neural Networks (IJCNN16)},
	year = {2016},
	month = {07/2016},
	address = {Vancouver, Canada},
	abstract = {In one-class classification problems, a model is synthesized by using only information coming from the nominal state of the data generating process. Many important applications can be cast in the one-class classification framework, such as anomaly and change in stationarity detection, and fault recognition. In this paper, we present a novel design methodology for oneclass classifiers derived from graph-based entropy estimators. The entropic graph is used to generate a partition of the input nominal conditions, which corresponds to the classifier model. Here we propose a criterion based on mutual information minimization to learn such a partition. The _-Jensen difference is considered, which provides a convenient way for estimating the mutual information. The classifier incorporates also a fuzzy model, providing a confidence value for a generic test sample during operational modality, expressed as a membership degree of the sample to the nominal conditions class. The fuzzification mechanism is based only on topological properties of the entropic spanning graph vertices; as such, it allows to model clusters of arbitrary shapes. We show preliminary {\textendash} yet very promising {\textendash} results on both synthetic problems and real-world datasets for one-class classification.
},
	author = {Livi, Lorenzo and Alippi, Cesare}
}
@conference {18489,
	title = {Secure architectures of future emerging cryptography},
	booktitle = {International Conference on Computing Frontiers CF{\textquoteright}16},
	series = {Proceedings of the ACM International Conference on Computing Frontiers},
	year = {2016},
	month = {05/2016},
	pages = {315-322},
	publisher = {ACM New York},
	organization = {ACM New York},
	address = {Como, italy},
	abstract = {Funded under the European Union{\textquoteright}s Horizon 2020 research and innovation programme, SAFEcrypto will provide a new generation of practical, robust and physically secure post-quantum cryptographic solutions that ensure long-term security for future ICT systems, services and applications. The project will focus on the remarkably versatile field of Lattice-based cryptography as the source of computational hardness, and will deliver optimised public key security primitives for digital signatures and authentication, as well identity based encryption (IBE) and attribute based encryption (ABE). This will involve algorithmic and design optimisations, and implementations of lattice-based cryptographic schemes addressing cost, energy consumption, performance and physical robustness. As the National Institute of Standards and Technology (NIST) prepares for the transition to a post-quantum cryptographic suite B, urging organisations that build systems and infrastructures that require long-term security to consider this transition in architectural designs; the SAFEcrypto project will provide Proof-of-concept demonstrators of schemes for three practical real-world case studies with long-term security requirements, in the application areas of satellite communications, network security and cloud. The goal is to affirm Lattice-based cryptography as an effective replacement for traditional number-theoretic public-key cryptography, by demonstrating that it can address the needs of resource-constrained embedded applications, such as mobile and battery-operated devices, and of real-time high performance applications for cloud and network management infrastructures},
	keywords = {identity based encryption, lattice-based cryptography, physical attacks, public-key cryptography},
	isbn = {978-1-4503-4128-8},
	doi = {10.1145/2903150.2907756},
	url = {http://doi.acm.org/10.1145/2903150.2907756},
	author = {O{\textquoteright}Neill, Maire and O{\textquoteright}Sullivan, Elizabeth and McWilliams, Gavin and Saarinen, Markku-Juhani and Moore, Ciara and Khalid, Ayesha and Howe, James and Del Pino, Rafael and Abdalla, Michel and Regazzoni, Francesco and Valencia, Andres Felipe and G{\"u}neysu, Tim and Oder, Tobias and Waller, Adrian and Jones, Glyn and Barnett, Anthony and Griffin, Robert and Byrne, Andrew and Ammar, Bassem and Lund, David}
}
@conference {18379,
	title = {Proactive Failure Management in Smart Grids for Improved Resilience (A Methodology for Failure Prediction and Mitigation)},
	booktitle = {IEEE GLOBECOM SmartGrid Resilience (SGR) Workshop},
	year = {2015},
	month = {12/2015},
	address = {San Diego, CA, USA},
	abstract = {A gradual move in the electric power industry towards Smart Grids brings several challenges to the system operation such as preserving its resilience and ensuring security. As the system complexity grows and a number of failures increases, the need for grid management paradigm shift from reactive to proactive is apparent and can be realized by employing advanced monitoring instruments, data analytics and prediction methods. In order to improve resilience of the Smart Grid and to contribute to efficient system operation, we present a blueprint of a comprehensive methodology for proactive failure management that may also be applied to manage other types of disturbances and undesirable changes. The methodology is composed of three main steps: (i) continuous monitoring of the most indicative features, (ii) prediction of failures and (iii) their mitigation. The approach is complementary to the existing ones that are mainly based on fast detection and localization of grid disturbances, and reactive corrective actions.},
	keywords = {Failure Prediction, Proactive Management, Resilience, security, smart grid, Synchrophasor},
	author = {Kaitovi{\'c}, Igor and Lukovi{\'c}, Slobodan and Malek, Miroslaw}
}
@conference {18378,
	title = {Unifying Dependability of Critical Infrastructures: Electric Power System and ICT (Concepts, Figures of Merit and Taxonomy)},
	booktitle = {IEEE Pacific Rim International Symposium on Dependable Computing (PRDC)},
	year = {2015},
	month = {11/2015},
	address = {Zhangjiajie, China},
	abstract = {With Smart Grids efficiency of the electric power delivery service can be significantly increased by using advanced ICT infrastructure. The looming danger of merging two critical infrastructures, ICT and electric power, is that dependability may be compromised due to interdependencies and different approaches to dependability in the two communities. This calls for a unified approach to dependability which may be achieved by viewing Smart Grids as cyber-physical systems. We analyze and compare definitions and figures of merit used in ICT and electric power systems{\textquoteright} communities to provide the basis for dependability analysis of Smart Grids. We propose a taxonomy of faults for Smart Grids by examining a large set of previous power system outages. Our work relies on the analysis of relevant events from the past in an attempt to understand present dependability state of Smart Grids and pave the way for proactive grid management.},
	keywords = {Critical Infrastructures, Cyber-Physical, Dependability, Fault Taxonomy, smart grid},
	author = {Kaitovi{\'c}, Igor and Lukovi{\'c}, Slobodan and Malek, Miroslaw}
}
@conference {18296,
	title = {A Conceptual Solution for Integration of EV Charging with Smart Grids },
	booktitle = {International Conference on Smart Grid and Clean Energy Technologies - ICSGCE 2014 },
	year = {2014},
	month = {10/2014},
	address = {Dubai},
	abstract = {Coordinated charging of electric vehicles (EVs) represents one of important aspects of future smart grid
implementation. The main focus of the present work is on designing a conceptual architecture as a solution for
managing (mobile) electric storages utilization. The solution requires holistic approach which takes into consideration
all actors in power system management. Requirements and use-cases are specified, structural and behavioral models
are developed and presented. The ICT (Information and Communication Technologies) model of the architecture that
supports smart charging with dynamic pricing is developed using systems engineering methods. Results are verified
by means of system level simulations.},
	keywords = {dynamic pricing, electric vehicles, Smart charging, systems engineering},
	author = {Lukovi{\'c}, Slobodan and Miladinovic, Bojan}
}
@inbook {18024,
	title = {Modeling Responsiveness of Decentralized Service Discovery in Wireless Mesh Networks},
	booktitle = {MMB \& DFT},
	series = {Lecture Notes in Computer Science},
	volume = {8376},
	year = {2014},
	pages = {88-102},
	publisher = {Springer International Publishing Switzerland},
	organization = {Springer International Publishing Switzerland},
	abstract = {In modern service networks, discovery plays a crucial role as a layer where providing instances of a given service can be published and enumerated. Since successful discovery is mandatory for service usage, comprehensive service dependability assessment needs to incorporate the dependability of the discovery layer. This work focuses on the responsiveness of the discovery layer, the probability to operate successfully within a deadline, even in the presence of faults. It proposes a hierarchy of stochastic models for decentralized discovery and uses it to describe the discovery of a single service using three well-known discovery protocols: domain name system based service discovery (DNS-SD), simple service discovery protocol (SSDP) and service location protocol (SLP). Further, a methodology to use the model hierarchy in wireless mesh networks is introduced. Given a pair service requester and provider, a discovery protocol and a deadline, it estimates packet loss probabilities and transmission time distributions for each link on the communication paths between the pair, generates specific model instances and calculates the expected responsiveness. Finally, the paper introduces a new metric, the expected responsiveness distance d_er to estimate the maximum distance from a provider where requesters are still able to discover it with a required responsiveness. The models and their methodology are demonstrated using monitoring data from the distributed embedded systems (DES) testbed at Freie Universit{\"a}t Berlin. It is shown how the responsiveness and d_er of the protocols change depending on the position of requester and provider and the overall link quality in the network.},
	keywords = {fault tolerance, Markov Models, Real time systems, Responsiveness, Service Discovery, Wireless mesh networks},
	isbn = {978-3-319-05358-5},
	issn = {0302-9743},
	doi = {10.1007/978-3-319-05359-2_7},
	url = {http://andreas-dittrich.eu/2013/12/modeling-responsiveness-of-decentralized-service-discovery-in-wireless-mesh-networks},
	author = {Dittrich, Andreas and Lichtblau, Bj{\"o}rn and Rezende, Rafael and Malek, Miroslaw},
	editor = {Fischbach, K. and Krieger, U. R.}
}
@conference {18043,
	title = {Probabilistic Breadth-First Search {\textendash} A Method for Evaluation of Network-Wide Broadcast Protocols},
	booktitle = {6th IEEE/ACM/IFIP International Conference on New Technologies, Mobility and Security (NTMS)},
	year = {2014},
	month = {03/2014},
	publisher = {IEEE Computer Society},
	organization = {IEEE Computer Society},
	address = {Dubai, UAE},
	abstract = {In wireless mesh networks (WMNs), network-wide broadcasts (NWBs) are a fundamental operation, required by routing and other mechanisms that distribute information to all nodes in the network. However, due to the characteristics of wireless communication, NWBs are generally problematic. Optimizing them is thus a prime target when improving the overall performance and dependability of WMNs. Most of the existing optimizations neglect the real nature of WMNs and are based on simple graph models, which provide optimistic assumptions of NWB dissemination. On the other hand, models that fully consider the complex propagation characteristics of NWBs quickly become unsolvable due to their complexity. In this paper, we present the Monte Carlo method probabilistic breadth-first search (PBFS) to approximate the reachability of NWB protocols. PBFS simulates individual NWBs on graphs with probabilistic edge weights, which reflect link qualities of individual wireless links in the WMN, and estimates reachability over a configurable number of simulated runs. This approach is not only more efficient than existing ones, but further provides additional information such as the distribution of path lengths. Furthermore, it is easily extensible to NWB schemes other than flooding. The applicability of PBFS is validated both theoretically and empirically, in the latter by comparing reachability as calculated by PBFS and measured in a real-world WMN. Validation shows that PBFS quickly converges to the theoretically correct value and approximates the behaviour of real-life testbeds very well. The feasibility of PBFS to support research on NWB optimizations or higher level protocols that employ NWBs is demonstrated in two use cases.},
	keywords = {Monte Carlo methods, Network-wide broadcasts, Probabilistic network graphs, Wireless mesh networks},
	isbn = {9781479932238},
	doi = {10.1109/NTMS.2014.6814046},
	url = {http://andreas-dittrich.eu/2014/01/pbfs},
	author = {Lichtblau, Bj{\"o}rn and Dittrich, Andreas}
}
@conference {18251,
	title = {Smart Charging Cell for Smart Cities},
	booktitle = {The 2nd IEEE International Workshop on Intelligent Energy Systems (IWIES) },
	year = {2014},
	month = {08/2014},
	abstract = {Energy consumption can be to some extent steered not only in time but in special cases in space as well. This mostly concerns electric vehicles (EV) charging. In this work we present conceptual solution of a {\textquoteleft}GeoGreen Cell{\textquoteright} developed in scope of an international project {\textendash} Ge(o)Green. The main purpose of such an aggregation is to efficiently coordinate. EV charging with respect to price of energy both in time and space. Even though massive acceptance of EVs seems far, there is an emerging need for conceptual solutions and reference models of solutions for their seamless integration into energy system in particular in urban areas. In fact, system level models of the supporting ICT architecture, including structural and behavioral ones, have been
developed. The models have been verified by means of simulations to assure their correctness. Scheduling optimization algorithms have been created and the system has been validated by means of system-level simulations.},
	keywords = {aggregation, EV charging, structural and behavioral models, SyML},
	author = {Lukovi{\'c}, Slobodan and Kaitovi{\'c}, Igor}
}
@conference {17770,
	title = {Adapting Multi-Agent Systems Approach for Integration of Prosumers in Smart Grids},
	booktitle = {Proceedings of the IEEE Eurocon 2013},
	year = {2013},
	month = {July},
	abstract = {Massive deployment of distributed energy resources, predominately renewable, is expected to be a general trend in the near future. Integration of such elements in distribution grid represents one of key challenges that Smart Grids will have to face with. In this work we aim at bridging
industrial and academic views on future trends in this field. We list main issues to be tackled and we propose a conceptual system-level solution based on Multi-Agent Systems. We show basic functionalities and structure for supporting ICT architecture.},
	author = {Lukovi{\'c}, Slobodan},
	editor = {Kovac, Boksov}
}
@conference {17741,
	title = {Calibration and in-Field Validation Tests of a Web-based Adaptive Management System for Monitoring - Scaphoideus titanus},
	booktitle = {Future Integrated Pest Management in Europe},
	year = {2013},
	abstract = {We developed a Web-based Adaptive Management System (WAMS) within a research project, called "SMART VINEYARD", which was funded by the Swiss Federal Commission for Technology and Innovation (Project 11307.1 PFES-ES). Goal of the project was to address the challenge of proposing a decision support system to provide real-time forecast of the life stages of - Scaphoideus titanus, vector of flavescence dor{\'e}e. The benefit of using the WAMS is to decide the timing of insecticide application and the planning of in-field monitoring tasks.},
	author = {Prevostini, Mauro and Taddeo, Antonio Vincenzo and Bala{\'c}, Katarina and Jermini, Mauro and Linder, Christian}
}
@conference {18039,
	title = {Smart Building Integration in Smart Grids},
	booktitle = {The 44th Heating Ventilation Air Condition and Refrigeration Congress and Exhibition - KGH 2013},
	year = {2013},
	abstract = {Modern power distribution systems gradually evolve into Smart Grids. Intelligence is getting inserted in all segments of the grid, monitoring and controlling entire power flow from generation and distribution down to consumption of home appliances. On the other hand renewable generation systems are getting widely deployed in public and residential buildings turning them into prosumers. Such scenario requires novel solutions for smart coupling of generation and consumption. Different kinds of prosumers clustering have been proposed by scientific community as a response. In the present work we propose an ICT structure capable of tackling this challenge. The conceptual solution represents an architecture which enables seamless integration of Smart Buildings into Smart Grids.},
	keywords = {Clustering, smart grid, smart home, System Level Model},
	author = {Lukovi{\'c}, Slobodan and {\v C}ongradac, Velimir and Kuli{\'c}, Filip}
}
@conference {18054,
	title = {STRATOS: open System for TRAcTOrs{\textquoteright} autonomous OperationS},
	booktitle = {EFITA Internation Conference on Sustainable Agriculture through ICT Innovation },
	year = {2013},
	month = {06/2013},
	publisher = {European Federation for Information Technology in Agriculture, Food and the Environment},
	organization = {European Federation for Information Technology in Agriculture, Food and the Environment},
	address = {Torino, Italy},
	abstract = {This paper describes the objectives and final results of the STRATOS project (System for TRAcTOrs{\textquoteright} autonomous OperationS), within the framework of ICT-AGRI ERA-NET (Coordination of European Research within ICT and Robotics in Agriculture and related Environmental Issues). The main objective of the STRATOS project was the development of an open ICT hardware-software infrastructure enabling the acquisition of geo-referenced information on soil and terrain parameters. In more detail, STRATOS project target was to develop and demonstrate new functions enabled by ISOBUS technology (ISO 11783) that support a substantial improvement of the quality of the farming jobs. In particular the idea is to develop a technology based on ISOBUS compliant, wireless self-powered sensor network for the real time measurement of soil and harvester conditions. In this way, Task Controller (an ICT component defined by ISOBUS specification which supervises actively the farming job performed by the tractor) can optimize the whole tractor and implement operational modes to improve the farming job quality and safety of the overall systems. The project lasted from 1st April, 2011 to31st March, 2013, and this paper reports about the project achievements.},
	keywords = {agriculture, ICT, model-driven approach, precision farming, Safety},
	author = {Fantuzzi, Cesare and Gutman, Per-Olof and Kaitovi{\'c}, Igor and Larcher, Luca and Marzani, Stefano and Ruggeri, Massimiliano and Zagurskis, Valerijs}
}
@inbook {18089,
	title = {Systems Engineering for Assessment of Virtual Power System Implementations},
	booktitle = {Artificial Intelligence Applications and Innovations},
	series = {9th IFIP WG 12.5 International Conference, AIAI 2013, Paphos, Cyprus, September 30 {\textendash} October 2, 2013, Proceedings},
	volume = {412},
	year = {2013},
	pages = {667-676},
	publisher = {Springer Berlin Heidelberg},
	organization = {Springer Berlin Heidelberg},
	abstract = {In this work we present an adoption of systems engineering methodology for design and assessment of a Virtual Power System (VPS). The VPS has been defined as an aggregation of distributed energy resources, consumers and storages which can operate autonomously, and is presented to the power system as a single unit in technical and commercial terms. The complexity of these critical systems is tackled by means of systems engineering. We have applied our approach in scope of a research project AlpEnergy.},
	keywords = {assessment, modeling, SysML, systems engineering, VPS},
	isbn = {978-3-642-41141-0},
	issn = {1868-4238},
	doi = {10.1007/978-3-642-41142-7_67},
	author = {Lukovi{\'c}, Slobodan and Kaitovi{\'c}, Igor}
}
@conference {18076,
	title = {LEXCOMM: A low energy, secure and flexible communication protocol for a heterogenous body sensor network},
	booktitle = {IEEE-EMBS International Conference on Biomedical and Health Informatics},
	year = {2012},
	month = {January},
	address = {Hong Kong, China},
	author = {Lamichhane, Bishal and Mudda, Steven and Regazzoni, Francesco and Puiatti, Alessandro}
}
@conference {18140,
	title = {STRATOS: Open System For Tractors{\textquoteright} Autonomous Operations},
	booktitle = {5th International Conference on Automation Technology for Off-road Equipment (ATOE)},
	year = {2012},
	month = {07/2012},
	pages = {162-187},
	publisher = {International Commission of Agricultural and Biosystems Engineering (CIGR)},
	organization = {International Commission of Agricultural and Biosystems Engineering (CIGR)},
	address = {Valencia, Spain},
	abstract = {This paper describes the objectives and preliminary results of the STRATOS project (System for TRAcTOrs{\textquoteright} autonomous OperationS), within the framework of ICT-AGRI ERA-NET (Coordination of European Research within ICT and Robotics in Agriculture and related Environmental Issues). The main objective of the STRATOS project is to develop an open ICT hardware-software infrastructure enabling the partial automation of tractors and at the same time enhancing their operational safety and production efficiency, with the positive effects of reduced accident risk and environmental impact. In more detail, STRATOS project target is to develop and demonstrate new functions enabled by ISOBUS technology (ISO 11783) that support a substantial improvement of the quality of the farming jobs. In particular the idea is to develop a technology based on ISOBUS compliant, wireless self-powered sensor network for the real time measurement of soil and harvester conditions. In this way, Task Controller (an ICT component defined by ISOBUS specification which supervises actively the farming job performed by the tractor) can optimize the whole tractor and implement operational modes to improve the farming job quality and safety of the overall systems. The project started on 1 st April, 2011, and will end the 31 st March, 2013, This paper reports about some achievement gained so far.},
	keywords = {agriculture, ICT infrastructure Design, model-driven approach, precision farming, Safety},
	isbn = {84-615-9654-4},
	author = {Fantuzzi, Cesare and Gutman, Per-Olof and Kaitovi{\'c}, Igor and Larcher, Luca and Marzani, Stefano and Ruggeri, Massimiliano and Zagurskis, Valerijs}
}
@conference {17766,
	title = {System Level Approach to Denial-of-Service Detection in MPSoCs},
	booktitle = {Proceedings of the 7th Workshop on Embedded Systems Security (WESS{\textquoteright}2012), A Workshop of the Embedded Systems Week (ESWEEK{\textquoteright}12)},
	year = {2012},
	month = {10/2012},
	abstract = {Multiprocessor Systems-on-Chip (MPSoCs) are pervading our lives, acquiring ever increasing relevance in a large number of applications, including even safety-critical ones. MPSoCs, are becoming increasingly complex and heterogeneous; the increased complexity as well as the networking approach in turn make security aspects more critical. In this work we propose and implement a hierarchical multi-agent approach providing solutions to secure Network-on-Chip based MPSoCs at different levels of design from nondeterministic attacks such as Denial-of-Service (DoS). We develop a flexible, scalable and modular structure integrating protection of different elements in the MPSoC (e.g. memory, processors) that can be tuned to particular attack scenarios - in this case a DoS attack. This work aims at providing a comprehensive, system-level protection strategy: this constitutes its main methodological contribution. We prove feasibility of the concepts via prototype realization in FPGA technology.},
	author = {Lukovi{\'c}, Slobodan and Srivastava, Anubhav}
}
@conference {159.LuVuKaEr12.MELECON,
	title = {Virtual Metering for Virtual PHEV Aggregation},
	booktitle = {Proceedings of the 16th IEEE Mediterranean Electrotechnical Conference (MELECON2012)},
	year = {2012},
	month = {March 25-28},
	address = {Yasmine Hammamet, Tunisia},
	abstract = {Technically sustainable solutions for integration of (PH)EVs in Smart Grid emerge as an important concern. We discuss the need for introduction of Virtual Aggregations supported by implementation of Virtual Meters in power system structures. We advocate our proposal with an evaluation of scenarios based on realistic data. The structure and functionalities of the Virtual Aggregator, as well as proposed enhancements on the Smart Grid side, are presented.},
	author = {Lukovi{\'c}, Slobodan and Vukmirovi{\'c}, Srdjan and Kaitovi{\'c}, Igor and Erdeljan, Aleksandar}
}
@conference {150.KaLu11,
	title = {Adoption of Model-Driven methodology to aggregations design in Power Grid},
	booktitle = {INDIN {\textquoteright}11: Proceedings of the 9th IEEE International Conference on Industrial Informatics},
	year = {2011},
	month = {July 26-29},
	pages = {1{\textendash}6},
	address = {Caparica, Lisbon, Portugal},
	abstract = {Economical and environmental concerns push toward novel solutions for sustainable, renewable and intelligent energy power grid, the Smart Grid. Very often, this includes aggregation of renewable resources and intelligent loads such as electrical vehicles. Such complex system involve a number of various stakeholders coming from different areas of expertise. Even so, on-going projects do not apply unique formal language. In order to better correlate the projects, model-driven methodology and SysML are proposed for system design.},
	keywords = {EVs agregation, model-driven design, smart grid, SysML},
	doi = {http://dx.doi.org/10.1109/INDIN.2011.6034936},
	author = {Kaitovi{\'c}, Igor and Lukovi{\'c}, Slobodan}
}
@inbook {141.aetherinbook.2011,
	title = {AETHER: Self-Adaptive Networked Entities: Autonomous Computing Elements for Future Pervasive Applications and Technologies},
	booktitle = {Reconfigurable Computing: From FPGAs to Hardware/Software Codesign},
	year = {2011},
	pages = {149{\textendash}184},
	publisher = {Springer},
	organization = {Springer},
	address = {New York, USA},
	abstract = {The AETHER project has laid the foundation of a complete new framework for designing and programming computing resources that live in changing environments and need to re-configure their objectives in a dynamic way. This chapter contributes to a strategic research agenda in the field of self-adaptive computing systems. It brings inputs to the reconfigurable hardware community and proposes directions to go for reconfigurable hardware and research on self-adaptive computing; it tries to identify some of the most promising future technologies for reconfiguration, while pointing out the main foreseen Challenges for reconfigurable hardware. This chapter presents the main solutions the AETHER project proposed for some of the major concerns in trying to engineer a self-adaptive computing system. The text exposes the AETHER vision of self-adaptation and its requirements. It describes and discusses the proposed solutions for tackling self-adaptivity at the various levels of abstractions. It exposes how the developed technologies could be put together in a real methodology and how self-adaptation could then be used in potential applications. Finally and based on lessons learned from AETHER, we discuss open issues and research opportunities and put those in perspective along other investigations and roadmaps.},
	isbn = {978-1-4614-0061-5},
	author = {Gamrat, Christian and Philippe, Jean-Marc and Jesshope, Chris and Shafarenko, Alex and Bisdounis, Labros and Bondi, Umberto and Ferrante, Alberto and Cabestany, Joan and Huebner, Michael and Parsinnen, Juha and Kadlec, Jiri and Danek, Martin and Tain, Benoit and Eisenbach, Susan and Auguin, Michel and Diguet, Jean-Philippe and Lenormand, Eric and Roux, Jean-Luc},
	editor = {Cardoso, Joao Manuel Pai and Huebner, Michael}
}
@conference {152.KrLeAhPoLi11.SiPS,
	title = {Beamforming for interference mitigation and its implementation on an SDR baseband processor},
	booktitle = {SiPS{\textquoteright}11: Proceedings of the IEEE Workshop on Signal Processing Systems},
	year = {2011},
	month = {October 4-7},
	pages = {1{\textendash}6},
	address = {Beirut, Lebanon},
	abstract = {We present the first implementation of a distributed beamforming algorithm for interference mitigation on an SDR baseband processor. Co-channel interference (CCI) is becoming a major source of impairments in wireless communications and distributed beamforming is a promising technique to mitigate its negative impact. However, such schemes are challenging to implement in practical scenarios due to their complexity and synchronization requirements. In this paper, we report on implementation of a suboptimal, yet efficient, beamforming scheme for CCI mitigation and present the complexity modeling and algorithm transformations for achieving numerically stability. We also present the fixed-point quantization and the proper mapping on a parallel programmable baseband architecture aimed for software-defined radio (SDR). We optimize this algorithm for a coarse grained reconfigurable array (CGRA) processor and evaluate it in the context of the LTE standard.},
	keywords = {beamforming, coarse grained reconfigurable array (CGRA), fixed-point arithmetic, long term evolution (LTE), software defined radio (SDR)},
	doi = {http://dx.doi.org/10.1109/SiPS.2011.6088973},
	author = {Krdu, Adrian and Lebrun, Yann and Ahmad, Ubaid and Pollin, Sofie and Li, Min}
}
@article {18063,
	title = {Harvesting the potential of nano-CMOS for lightweight cryptography: An ultra-low-voltage 65 nm AES coprocessor for passive RFID tags},
	journal = {Springer Journal of Cryptographic Engineering},
	volume = {1},
	issue = {1},
	year = {2011},
	author = {Hocquet, C{\'e}dric and Kamel, Dina and Regazzoni, Francesco and Legat, Jean-Didier and Flandre, Denis and Bol, David and Standaert, Fran{\c c}ois-Xavier}
}
@conference {18081,
	title = {Power-Gated MOS Current Mode Logic (PG-MCML): A Power-Aware DPA-Resistant Standard Cell Library},
	booktitle = {48th Design Automation Conference (DAC)},
	year = {2011},
	month = {June},
	address = {San Diego, Califorina},
	author = {Cevrero, Alessandro and Regazzoni, Francesco and Schwander, Michael and Badel, St{\'e}phane and Ienne, Paolo and Leblebici, Yusuf}
}
@inbook {160.MuSaLuMa.2011,
	title = {Progettazione e valutazione di soluzioni wireless multi-hop per il monitoraggio ambientale},
	booktitle = {MIARIA: Techologia e Conoscenza al Servizio della Sicurezza},
	year = {2011},
	pages = {108-120},
	publisher = {Bellavite},
	organization = {Bellavite},
	address = {Missaglia, Italy},
	abstract = {The creation of a sensors network for environmental monitoring, taking into account the functional and non-functional requirements, poses a series of problems that must be dealt with during the design phase. The main difficulties are related to the power of the nodes and their location so that the resulting network topology minimizes the overall energy consumption while guaranteeing the desired measurement accuracy. The adoption of a {\textquoteright}wireless{\textquoteright} communication model allows for greater flexibility during installation and allows creating remote connections more easily than the traditional wired pattern. Extension of the network topology by add ing new devices in the monitoring area or movement of devices already deployed are greatly simplified. But the requirements in terms of fault-tolerance and power consumption of a wireless network are in general more difficult to meet. In this chapter we propose two different solutions that improve performance in terms of power consumption of the main standard for communication in wireless sensor networks field (e.g. ZigBee) customizing it for monitoring applications in an open environment on geographical areas of several hectares. While the standard is intended to be as general as possible, optimizations have been included considering the special needs of our monitoring applications, in terms of number of nodes, topology density, nodes duty cycle and data-load. The first solution deals with the management of multi-hop communication and allows the use of devices that can be powered by batteries (and possibly small solar panels) for the relaying nodes. The second solution optimizes the management of faults (transient or permanent) in the network topology. It is rarely possible to develop and evaluate proposed solutions in the field prior to actual deployment, therefore simulation is an essential step in developing solutions for these applications. The simulation must be accurate and must provide an analysis of all issues related to communication and the behavioural dynamics of the single node in the network structure. For this reason the evaluation has been carried out by means of a modelling methodology developed expressly for wireless sensor networks.},
	isbn = {978-88-7511-164-9},
	author = {Mura, Marcello and Sami, Mariagiovanna and Luppi, Alessandro and Malchiodi, Gianluca}
}
@conference {17740,
	title = {Towards an ESL design framework for adaptive and fault-tolerant MPSoCs: MADNESS or not?},
	booktitle = {Embedded Systems for Real-Time Multimedia (ESTIMedia), 2011 9th IEEE Symposium on},
	year = {2011},
	abstract = {The MADNESS project aims at the definition of innovative system-level design methodologies for embedded MP-SoCs, extending the classic concept of design space exploration in multi-application domains to cope with high heterogeneity, technology scaling and system reliability. The main goal of the project is to provide a framework able to guide designers and researchers to the optimal composition of embedded MPSoC architectures, according to the requirements and the features of a given target application field. The proposed approach will tackle the new challenges, related to both architecture and design methodologies, arising with the technology scaling, the system reliability and the ever-growing computational needs of modern applications. The methodologies proposed with this project act at different levels of the design flow, enhancing the state-of-the art with novel features in system-level synthesis, architectural evaluation and prototyping. Support for fault resilience and efficient adaptive runtime management is introduced at hardware and middleware level, and considered by the system-level synthesis as one of the optimization factors to be taken into account. This paper presents the first stable results obtained in the MADNESS project, already demonstrating the effectiveness of the proposed methods.},
	keywords = {adaptive MPSoC, adaptive runtime management, computer architecture, embedded MPSoC architectures, emulation, ESL design framework, fault resilience, fault tolerance, fault tolerant MPSoC, field programmable gate arrays, hardware, integrated circuit reliability, libraries, MADNESS project, middleware, multiprocessing systems, network synthesis, program processors, system level design methodologies, system level synthesis, system reliability, system-on-chip (SoC)},
	doi = {10.1109/ESTIMedia.2011.6088518},
	author = {Cannella, Emanuele and Di Gregorio, Lorenzo and Fiorin, Leandro and Lindwer, Menno and Meloni, Paolo and Neugebauer, Olaf and Pimentel, Andy}
}
@conference {124.LuKaBo10,
	title = {Adopting system engineering methodology to Virtual Power Systems design flow},
	booktitle = {CPSWEEK/GREEMBED 2010: Proceedings of the First Workshop on Green and Smart Embedded System Technology: Infrastructures, Methods and Tools},
	year = {2010},
	month = {April},
	address = {Stockholm, Sweden},
	abstract = {The concept of Virtual Power System (VPS) emerges as a promising response for increased concerns on secure, sustainable and at the same time {\textquoteright}clean{\textquoteright} energy supply requests. This novel concept aims at boosting operational efficiency of Distributed Energy Resources (DER) but also at establishing them as an autonomous commercial actor on the open energy market. Nevertheless, VPSs are fairly complex HW/SW systems that require holistic multidisciplinary approach and also novel specification, modeling and analysis instruments to facilitate mutual understanding among stakeholders from different fields. We introduce UML/SysML based modeling methodology to describe such power system related issues aiming at providing an unified modeling instrument applicable for VPSs design flow. In the proposed system engineering methodology, system representation starts from a very general context description and gets refined through different levels of abstraction down to concrete embedded systems employed to perform defined tasks.},
	author = {Lukovi{\'c}, Slobodan and Kaitovi{\'c}, Igor and Bondi, Umberto}
}
@conference {114.MaYkZhZhLa10,
	title = {An Efficient Run-Time Management Methodology for Stereo Matching Application},
	booktitle = {2PARMA: Proceedings of the Workshop on Parallel Programming and Run-time Management Techniques for Many-core Architectures},
	year = {2010},
	month = {February},
	address = {Hannover, Germany},
	abstract = {This paper presents a methodology for Run-Time Management (RTM) of algorithmic parameters. The RTM is able to trade-off the algorithm output quality and the execution time. Thus, once a requirement in terms of maximum execution time is set, the RTM dynamically tunes the parameters in order to maximize the output quality while respecting the given requirement. The run-time decision making relies on design-time modeling techniques able to characterize key relations between algorithm parameters, execution time and output quality. Models generated during the design-time analysis are accurate enough to drive the RTM in its decision making while enough generic to model application behaviors over datasets which were not included at design-time. In this paper the methodology is applied on the Stereo Matching application, a computational intensive artificial vision application aimed at inferring object depths using two or more cameras. Experimental results prove the effectiveness of the methodology which is able to identify high quality solutions respecting required deadline while introducing negligible overhead.},
	author = {Mariani, Giovanni and Ykman-Couvreur, Chantal and Zhang, Ke and Zhang, Lu and Lafruit, Gauthier}
}
@conference {135.VuLuErKu10.2,
	title = {An enhanced workflow management for Utility Management System},
	booktitle = {Proceedings of the International Congress on Ultra Modern Telecommunications and Control Systems (ICUMT 2010)},
	year = {2010},
	month = {October 18-20},
	address = {Moscow, Russia},
	abstract = {The emerging computational grid infrastructure consists of widely distributed heterogeneous resources, which makes mapping of increasingly complex applications a very challenging task. Utility Management Systems (UMS) manage very large number of workflows with very high resource requirements and thereby optimization of resource utilization has to be adapted. In this work we propose architecture that implements a novel concept for dynamical execution of a scheduling algorithm using near real-time feedback from the execution monitoring process. An Artificial Neural Network (ANN) was trained for workflow scheduling. In the case study, we first perform experiments with same number of workflows and then introduce two additional in the system observing its behavior with and without proposed improvements. Performance tests show that significant improvements of overall execution time can be achieved by introducing adaptive Artificial Neural Network.},
	doi = {http://dx.doi.org/10.1109/ICUMT.2010.5676601},
	author = {Vukmirovi{\'c}, Srdjan and Lukovi{\'c}, Slobodan and Erdeljan, Aleksandar and Kuli{\'c}, Filip}
}
@conference {133.LuNi10.2,
	title = {Enhancing Network-on-Chip Components to Support Security of Processing Elements},
	booktitle = {Proceedings of the 5th Workshop on Embedded Systems Security (WESS{\textquoteright}2010) A Workshop of the Embedded Systems Week (ESWEEK {\textquoteright}10)},
	year = {2010},
	month = {October 24},
	address = {Scottsdale, AZ, USA},
	abstract = {Network-on-Chip (NoC) has emerged as a promising solution for scalable communication among steadily growing number of cores integrated in MultiProcessor System-on-Chips (MPSoCs). The increasing system heterogeneity together with the possibility of recon guration makes the overall system security one of the major concerns in MPSoC design. On the other hand, modular and scalable design of NoCs enables their enhancements in various directions for supporting services other than simple data routing. In this work we propose and implement a solution to secure attached processing units from a bu er over ow type of the attacks that comes in a form of a protection module that is embedded into the Network Interface of the NoC. At the same time, our solution prevents potential propagation of the attack through the NoC towards other processors. We prove feasibility via prototype realization in FPGA technology for a MicroBlaze processor on Xilinx Virtex-II Pro board.},
	doi = {http://dx.doi.org/10.1145/1873548.1873560},
	author = {Lukovi{\'c}, Slobodan and Christianos, Nikolaos}
}
@conference {130.LuKaMuBoKuPo10,
	title = {Functional model of Virtual Power Plant (VPP)},
	booktitle = {Proceedings of the 2010 CIGRE (International Council on Large Electric Systems) Session},
	year = {2010},
	month = {July},
	address = {Paris, France},
	keywords = {smart grid, unified modeling language (UML), virtual power plants},
	author = {Lukovi{\'c}, Slobodan and Kaitovi{\'c}, Igor and Mura, Marcello and Bondi, Umberto and Kuli{\'c}, Filip and Popovi{\'c}, Dragan}
}
@conference {132.LuNi10,
	title = {Hierarchical Multi-Agent Protection System for NoC based MPSoCs},
	booktitle = {Proceedings of the International Workshop on Security and Dependability for Resource Constrained Embedded Systems (SD4RCES 2010)},
	year = {2010},
	month = {September 14},
	address = {Vienna, Austria},
	abstract = {Network-on-Chip (NoC) has emerged as a promising solution for scalable communication among steadily growing number of cores integrated in MultiProcessor System-on-Chips (MPSoCs). The increasing system heterogeneity together with the possibility of reconfiguration makes the overall system security one of the major concerns in MPSoC design. On the other hand, modular and scalable design of NoCs enables their enhancements in various directions for supporting services other than simple data routing. In this work we propose a conceptual solution to secure NoC based MPSoCs at different levels of design. The basic idea is to integrate various kinds of security approaches from attack specific protection strategies up to system level security. The concept aims at securing single cores but also, at the same time, prevents potential propagation of the attack through the NoC towards. We prove feasibility via prototype realization in FPGA technology.},
	keywords = {multiprocessor system-on-chip (MPSoC), network-on-chip (NoC), security},
	doi = {http://dx.doi.org/10.1145/1868433.1868441},
	author = {Lukovi{\'c}, Slobodan and Christianos, Nikolaos}
}
@conference {137.VuLuErKu10.3,
	title = {A Smart Metering Architecture as a step towards Smart Grid realization},
	booktitle = {Proceedings of the IEEE EnergyCon 2010},
	year = {2010},
	month = {December 18-22},
	address = {Bahrain},
	abstract = {Emerging concept of Smart Grids aims at increasing visibility and controllability of electricity grids boosting their operational efficiency, enabling novel enhanced services to customers and utilities at a same time. Successful realization of this concept will in great part depend on efficient management of tremendous amounts of data to be gathered and processed in very short time periods. In this work we propose a novel smart metering architecture to manage data collected from deployed smart meters logically encapsulated in form of virtual meters. The metering infrastructure is structured in the form of Advanced Metering Infrastructure (AMI). The architecture of Meter Data Management (MDM) system as well and its integration in Control Center structure of power system is described in details. The testing and verification of proposed solution is performed on data from power distribution company Vattenfall, Sweden.},
	doi = {http://dx.doi.org/10.1109/ENERGYCON.2010.5771705},
	author = {Vukmirovi{\'c}, Srdjan and Lukovi{\'c}, Slobodan and Erdeljan, Aleksandar and Kuli{\'c}, Filip}
}
@conference {122.VuErKuLu10,
	title = {Software architecture for Smart Metering systems with Virtual Power Plant},
	booktitle = {Proceedings of the 15th IEEE Mediterranean Electrotechnical Conference (MELECON2010)},
	year = {2010},
	month = {April},
	address = {La Valleta, Malta},
	abstract = {This paper presents a novel architecture for Smart Metering systems which enables their seamless, secure and efficient integration in wider SmartGrid software structures. Smart metering solutions represent one of the fastest evolving areas in the field of power distribution systems. There is an extensive interest of leading software vendors in the field, for development of architectures that can efficiently manage transmission, processing and storing of tremendous amount of data produced by such metering devices deployed at the end-end side. The integration of these systems into existing power system software architectures (outage management, workforce management, etc.) represents a major challenge for research community. In such an environment it is extremely important to adopt standardized data exchange mechanisms. The proposed architecture is conceived as modular and scalable structure so that it can help implementation of novel power distribution concepts such as Virtual Power Plants (VPPs). The proposed architecture has been successfully tested and verified in real-life operation as one of modules of Smart Metering system named Meter Data Management (MDM) developed by Telvent DMS Llc, Serbia.},
	doi = {http://dx.doi.org/10.1109/MELCON.2010.5476237},
	author = {Vukmirovi{\'c}, Srdjan and Erdeljan, Aleksandar and Kuli{\'c}, Filip and Lukovi{\'c}, Slobodan}
}
@conference {131.VuLuErKu10,
	title = {A solution for CIM based integraton of Meter Data Management in Control Center of a power system},
	booktitle = {Proceedings of the 2010 IEEE Workshop on Environmental, Energy, and Structural Monitoring Systems (EESMS{\textquoteright}10)},
	year = {2010},
	month = {September 9},
	address = {Taranto, Italy},
	abstract = {Modern power systems, in particular Control Center structures, involve more and more software applications in their normal operation. Such scenario urges for standardization of inter and intra processes communication and data exchange. In this work we propose a solution for seamless Meter Data Management (MDM) integration with Control Center structures through Common Information Model (CIM). The solution is implemented in form of a wrapper that adopts messages (i.e. payloads) to the standard requested form. The proposed solution has been verified using a simulation framework which emulates regular control and data.},
	keywords = {monitoring and control, system level modeling, virtual power plants},
	doi = {http://dx.doi.org/10.1109/EESMS.2010.5634169},
	author = {Vukmirovi{\'c}, Srdjan and Lukovi{\'c}, Slobodan and Erdeljan, Aleksandar and Kuli{\'c}, Filip}
}
@conference {123.LuPeFi10,
	title = {Stack Protection Unit as a step towards securing MPSoCs},
	booktitle = {Proceedings of 24th IEEE International Parallel and Distributed Processing Symposium (IPDPS)},
	year = {2010},
	month = {April 19-23},
	address = {Atlanta, USA},
	abstract = {Reconfigurable technologies are getting popular as an instrument for not only verification and prototyping but also commercial implementation of Multi-Processor Systems-on-Chip (MPSoC) architectures. At the same time, these systems in particular Networks-on-Chip (NoCs) based ones, have emerged as a design strategy to cope with increased requirements and complexity of modern applications. Nevertheless, increasing heterogeneity coupled with possibility of reconfiguration makes security become one of major concerns in MPSoC design. Protection strategies must consider attack scenarios at both levels - individual cores and system level security. This work represents an element in a wider security framework, it shows a solution against one of the most widespread types of attacks - code injection. Our response to tackle this challenge is given in form of Stack Protection Unit (SPU) embedded into processing core. MicroBlaze soft-core processor serves as a case study for verification of the proposed solution in FPGA technology.},
	keywords = {FPGA, microblaze, security, stack protection unit},
	doi = {http://dx.doi.org/10.1109/IPDPSW.2010.5470728},
	author = {Lukovi{\'c}, Slobodan and Pezzino, Paolo and Fiorin, Leandro}
}
@conference {113.LuCoKu10,
	title = {A system level model of possible integration of Building Management System in SmartGrid},
	booktitle = {Complexity in Engineering (COMPENG 2010)},
	year = {2010},
	month = {February 22-24},
	address = {Rome, Italy},
	abstract = {SmartGrids are conceived as modular, end-to-end interoperable systems. It is envisaged that power systems components (modules) will be hierarchically coordinated and integrated in order to form certain autonomous clusters which would perform as much as possible local data storing and processing in order to decrease overall communicational and computational overhead. Building Management Systems (BMS) could be seen as one of such modules inside wider SmartGrid system. The incorporation of BMS must consider both technical as well as commercial issues. Hence, the efficient integration will require standards{\textquoteright} harmonization and closer interaction among key elements of these systems. Moreover, another important issue will be adopting of new market models to BMS. In order to represent the system and relations among its components in a clear and understandable fashion, we introduce system level modeling concept as an instrument to bridge functional requirements and implementation constraints.},
	doi = {http://dx.doi.org/10.1109/COMPENG.2010.43},
	author = {Lukovi{\'c}, Slobodan and {\v C}ongradac, Velimir and Kuli{\'c}, Filip}
}
@conference {118.CaVeStShCeLeAsMe10,
	title = {Trace-based KPN Composability Analysis for Mapping Simultaneous Applications to MPSoC Platforms},
	booktitle = {Proceedings of Design, Automation and Test in Europe(DATE) Conference},
	year = {2010},
	month = {March},
	address = {Dresden, Germany},
	abstract = {Nowadays, most embedded devices need to support multiple applications running concurrently. In contrast to desktop computing, very often the set of applications is known at design time and the designer needs to assure that critical applications meet their constraints in every possible use-case. In order to do this, all possible use-cases, i.e. subset of applications running simultaneously, have to be verified thoroughly. An approach to reduce the verification effort, is to perform composability analysis which has been studied for sets of applications modeled as Synchronous Dataflow Graphs. In this paper we introduce a framework that supports a more general parallel programming model based on the Kahn Process Networks Model of Computation and integrates a complete MPSoC programming environment that includes: compilercentric analysis, performance estimation, simulation as well as mapping and scheduling of multiple applications. In our solution, composability analysis is performed on parallel traces obtained by instrumenting the application code. A case study performed on three typical embedded applications, JPEG, GSM and MPEG-2, proved the applicability of our approach.},
	author = {Castrill{\'o}n, Jer{\'o}nimo and Vel{\'a}squez, Ricardo and Stulova, Anastasia and Sheng, Weihua and Ceng, Jianjiang and Leupers, Rainer and Ascheid, Gerd and Meyr, Heinrich}
}
@conference {112.LuKaMuBo10,
	title = {Virtual Power Plant as a bridge between Distributed Energy Resources and Smart Grid},
	booktitle = {Proceedings of 43th Hawaii International Conference on System Sciences (HICSS{\textquoteright}43)},
	year = {2010},
	month = {January},
	address = {Hawaii, USA},
	abstract = {The liberalization of energy markets, especially in correlation with the Smart Grid concept development, requires adjusted legislation, new business models, energy stock exchanges establishment and many other advanced instruments. Realization of these features necessitates novel concepts to support such changes in the power system while granting security and reliability of supply. Such evolution poses new challenges to ICT (Information and Communication Technologies) to bridge the gap between increased complexity of deregulated market and on the other side expected rapid growth of number of players in power systems. Increasing presence of Distributed Energy Resources (DER) implementations constitutes a further source of complexity. Bearing in mind ongoing and possible scenarios we aim to determinate the place and role of the novel Virtual Power Plants (VPP) concept, related to the Smart Grid structure. At the same time we introduce an innovative modeling approach as an instrument to determine actors and highlight their actual roles and interactions from different point of view, trying to pave the way for development of a common understanding platform for variety of stakeholders. The effectiveness of the proposed modeling concept is shown through a number of UML models representing system level description of VPP at different levels of abstraction.},
	keywords = {distributed energy resources, smart grid, unified modeling language (UML), virtual power plants},
	doi = {http://dx.doi.org/10.1109/HICSS.2010.437},
	author = {Lukovi{\'c}, Slobodan and Kaitovi{\'c}, Igor and Mura, Marcello and Bondi, Umberto}
}
@conference {18084,
	title = {The Certicom Challenges ECC2-X},
	booktitle = {Workshop on Special Purpose Hardware for Attacking Cryptographic Systems (SHARCS)},
	year = {2009},
	month = {September},
	address = {Lausanne, Switzerland},
	author = {Bailey, Daniel V. and Baldwin, Brian and Batina, Lejla and Bernstein, Daniel J. and Birkner, Peter and Bos, Joppe W. and van Damme, Gauthier and de Meulenaer, Giacomo and Fan, Junfeng and Gurkaynak, Frank and G{\"u}neys, Tim and Kleinjung, Thorsten and Lange, Tanja and Mentens, Nele and Paar, Christof and Regazzoni, Francesco and Schwabe, Peter and Uhsadel, Leif}
}
@inbook {18085,
	title = {A Design Flow and Evaluation Framework for DPA-resistant Instruction Set Extensions},
	booktitle = {Cryptographic Hardware and Embedded Systems (CHES)},
	series = {Lecture Notes in Computer Science},
	volume = {5747},
	year = {2009},
	month = {September},
	pages = {205-219},
	publisher = {Springer Berlin Heidelberg},
	organization = {Springer Berlin Heidelberg},
	address = {Lausanne, Switzerland},
	abstract = {Power-based side channel attacks are a significant security risk, especially for embedded applications. To improve the security of such devices, protected logic styles have been proposed as an alternative to CMOS. However, they should only be used sparingly, since their area and power consumption are both significantly larger than for CMOS. We propose to augment a processor, realized in CMOS, with custom instruction set extensions, designed with security and performance as the primary objectives, that are realized in a protected logic. We have developed a design flow based on standard CAD tools that can automatically synthesize and place-and-route such hybrid designs. The flow is integrated into a simulation and evaluation environment to quantify the security achieved on a sound basis. Using MCML logic as a case study, we have explored different partitions of the PRESENT block cipher between protected and unprotected logic. This experiment illustrates the tradeoff between the type and amount of application-level functionality implemented in protected logic and the level of security achieved by the design. Our design approach and evaluation tools are generic and could be used to partition any algorithm using any protected logic style.},
	isbn = {978-3-642-04137-2},
	doi = {10.1007/978-3-642-04138-9_15},
	author = {Regazzoni, Francesco and Cevrero, Alessandro and Standaert, Fran{\c c}ois-Xavier and Badel, St{\'e}phane and Kluter, Theo and Brisk, Philip and Leblebici, Yusuf and Ienne, Paolo}
}
@article {18064,
	title = {Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology},
	journal = {Springer Transactions on Computational Science},
	volume = {5430},
	year = {2009},
	month = {February},
	pages = {230{\textendash}243},
	author = {Regazzoni, Francesco and Eisenbarth, Thomas and Poschmann, Axel and Groschdl, Johann and Gurkaynak, Frank and Macchetti, Marco and Toprak, Zeynep and Pozzi, Laura and Paar, Christof and Leblebici, Yusuf and Ienne, Paolo}
}
@conference {102.LuKaMuBo09,
	title = {Functional requirements of embedded systems for monitoring and control structure of Virtual Power Plants},
	booktitle = {Proceedings of the 2009 IEEE Workshop on Environmental, Energy, and Structural Monitoring Systems},
	year = {2009},
	month = {September},
	address = {Crema, Italy},
	abstract = {Efficient integration of distributed renewable generation into a reliable single entity in technical and commercial terms is one of key issues for successful realization of smart-grids. The novel concept of Virtual Power Plants (VPP) emerges to be promising response to these needs. ICT is the enabling technology for VPP implementation. In fact, an efficient monitoring and control system coupled with appropriate communication structure must be designed in a scalable and modular way so that full interoperability among components of the system is achieved. On top of that, Control Center applications take care of power flow optimization (production, consumption, ancillary services) and high-level applications (e.g. energy trading, Demand Side Management etc.). In this work we focus on functional requirements for realization of such concept by means of embedded systems.},
	keywords = {monitoring and control, system level modeling, virtual power plants},
	doi = {http://dx.doi.org/10.1109/EESMS.2009.5341320},
	author = {Lukovi{\'c}, Slobodan and Kaitovi{\'c}, Igor and Mura, Marcello and Bondi, Umberto}
}
@conference {110.CoKuLu09,
	title = {Prediction of the type of heating with EnergyPlus program and fuzzy logic},
	booktitle = {40th International Congress on Heating, Refrigerating and Air-conditioning (KGH Congress)},
	year = {2009},
	month = {12/2009},
	address = {Belgrade, Serbia},
	abstract = {The purpose of this work is prediction of the type of heating for the next few days in an office building using EnergyPlus program for simulation and fuzzy logic for determination. In this matter a program that binds weather forecast, created simulation model in EnergyPlus of a five story building in Belgrade, simulation in EnergyPlus and fuzzy logic, and as a result program gives the type of heating which is the most economic to use for the particular day, was built. Everything is done in the way of most efficient and rational use of energy.},
	author = {{\v C}ongradac, Velimir and Kuli{\'c}, Filip and Lukovi{\'c}, Slobodan}
}
@Patent {87.pat07301411.0-2413PATENT,
	title = {Programmable data protection device, secure programming manager system and process for controlling access to an interconnect network for an integrated circuit},
	number = {EP 20070301411},
	year = {2009},
	month = {04/2009},
	type = {Application},
	chapter = {EP 2043324 A1},
	abstract = {A data protection device for an interconnect network on chip (NoC) includes a header encoder that receives input requests for generating network packets. The encoder routes the input requests to a destination address. An access control unit controls and allows access to the destination address. The access control unit uses a memory to store access rules for controlling access to the network as a function of the destination address and of a source of the input request.},
	issn = {EP 2043324 A1},
	author = {Fiorin, Leandro and Palermo, Gianluca and Silvano, Cristina and Catalano, Valerio and Locatelli, Riccardo and Coppola, Marcello}
}
@conference {80.LuFi08,
	title = {An Automated Design Flow for NoC-based MPSoCs on FPGA},
	booktitle = {RSP 2008, The 19th IEEE/IFIP International Symposium on Rapid System Prototyping},
	year = {2008},
	month = {June 2-5},
	address = {Monterey, USA/CA},
	abstract = {Increased dynamics of the embedded devices market makes reduced time-to-market emerge as one of most challenging tasks in modern embedded system design. The complexity of Multiprocessor Systems-on-Chip (MPSoCs) rapidly increases and Networks-on-Chips (NoCs) have emerged as design strategy to cope with it. In order to allow fast generation of these platforms in the development phase, a full design flow is required. On the other hand, modern FPGAs provide the possibility for fast and low-cost prototyping, representing an efficient response to these needs. In this paper we present a framework, based on the Xilinx Embedded Development Kit (EDK) design flow, for the generation of MPSoCs based on NoCs. The tool provides system designers with the possibility to easily and quickly generate desired architectures that can be helpful for testing, debugging and verifying purposes. Our integrated design flow takes as input a textual description of the system and produces as final result a configuration bitstream file. The framework has been tested and verified on a Xilinx Virtex-II Pro board.},
	keywords = {FPGA, multiprocessor system-on-chip (MPSoC), network-on-chip (NoC), reconfigurable systems, security},
	doi = {http://dx.doi.org/10.1109/RSP.2008.31},
	author = {Lukovi{\'c}, Slobodan and Fiorin, Leandro}
}
@conference {81.sliceb08,
	title = {An Enhanced Service Provider Communication Interface with Client Priorization},
	booktitle = {proceedings of IEEE/WFMC International Conference on e-Business},
	year = {2008},
	month = {July 26-29},
	abstract = {With the increased dynamics of modern life, the efficiency and reliability of everyday services is emerging to be a fundamental concern. On the other hand, modern telecommunication technologies, like wireless Internet access, are penetrating all segments of our life. However, many every day activities and services still do not fully exploit new technologies. We propose an approach that enables increased deployment of E-commerce concepts in the fields where their usage was either small or negligible. Moreover, in the scope of the same concept, we introduce prioritization of clients in services where it was not commonly present to date. A solution for enhanced communication interface between service provider and customers is developed. As a case study, the system is designed and optimized for an implementation in a fast-food chain. The proposed solution is aiming at increasing of quality of service for customers, and at the same time increasing the operational efficiency of the provider. The main idea behind this approach is to enable customers to use their mobile devices, such as cell phones or PDAs, for browsing offered services or goods, viewing current service conditions and placing orders. We will detail mathematical model underneath and describe the implementation on both server and client side.},
	author = {Lukovi{\'c}, Slobodan and Puzovi{\'c}, Nikola and Stanisavljevi{\'c}, Milo{\v s}}
}
@Patent {78.pat20080134187PATENT,
	title = {Hardware scheduled SMP architectures},
	number = {US 11/947,278},
	year = {2008},
	month = {06/2008},
	type = {Application},
	chapter = {US 20080134187 A1},
	abstract = {A symmetric multiprocessor system employing a hardware constituted real-time operating system.},
	issn = {US 20080134187 A1},
	author = {Lajolo, Marcello and Nacul, Andre Costi and Regazzoni, Francesco}
}
@conference {76.FiLuPa08,
	title = {Implementation of a Reconfigurable Data Protection Module for NoC-based MPSoCs},
	booktitle = {Proceedings of the 21st IPDPS 2007 Reconfigurable Architecture Workshop (RAW), 21th IEEE International Parallel and Distributed Processing Symposium},
	year = {2008},
	month = {April},
	address = {Miami, USA/FL},
	abstract = {Security issues are emerging to be a basic concern in modern SoC development. Since in the field of on-chip interconnections the security problem continues to remain mostly an unexplored topic, this paper proposes a novel technique for data protection that uses the communication subsystem as basis. The proposed architecture works as a firewall managing the memory accesses on the basis of a lookup table containing the access rights. This module, called Data Protection Unit (DPU), has been designed for MPSoC architectures and integrated in the Network Interfaces near the shared memory. We implement the DPU inside an MPSoC architecture on FPGA and we add features to the module to be aware of dynamic reconfiguration of the system software. Starting from a general overview of our design down to components structure, we introduce the place and the role of the DPU module inside the system for a reconfigurable secure implementation of a MPSoC on FPGA. The description of the DPU concept, its implementation, and integration into the system are described in detail. Finally, the architecture is fully implemented on FPGA and tested on a Xilinx Virtex-II Pro board.},
	keywords = {data protection, FPGA, multiprocessor system-on-chip (MPSoC), network-on-chip (NoC), reconfigurable systems, security},
	doi = {http://dx.doi.org/10.1109/IPDPS.2008.4536514},
	author = {Fiorin, Leandro and Lukovi{\'c}, Slobodan and Palermo, Gianluca}
}
@article {84.AlGaSte2008,
	title = {Secure Memory Accesses on Networks-on-Chip},
	journal = {IEEE Transactions on Computers},
	volume = {57},
	number = {9},
	year = {2008},
	month = {September},
	pages = {1216-1229},
	abstract = {Security is gaining relevance in the development of embedded devices. Towards a secure system at each level of design, this paper addresses security aspects related to Network on Chip (NoC) architectures, foreseen as the communication infrastructure of next-generation embedded devices. In the context of NoC-based multiprocessor systems, we focus on the topic, not yet thoroughly faced, of data protection. In this paper, we present a secure NoC architecture composed of a set of Data Protection Units (DPUs) implemented within the Network Interfaces (NIs)1. The run-time configuration of the programmable part of the DPUs is managed by a central unit, the Network Security Manager (NSM). The DPU, similar to a firewall, can check and limit the access rights (none, read, write, or both) of processors accessing data and instructions in a shared memory. In particular, the DPU can distinguish between the operating roles (supervisor/user and secure/non secure) of the processing elements.We explore alternative implementations of the DPU and demonstrate how this unit does not affect the network latency if the memory request has the appropriate rights. We also focus on the dynamic updating of the DPUs to support their utilization in dynamic environments, and on the utilization of authentication techniques to increase the level of security.},
	keywords = {data protection, embedded systems, multiprocessor system-on-chip (MPSoC), network-on-chip (NoC), security},
	doi = {http://dx.doi.org/10.1109/TC.2008.69},
	author = {Fiorin, Leandro and Palermo, Gianluca and Lukovi{\'c}, Slobodan and Catalano, Valerio and Silvano, Cristina}
}
@conference {61.PaMaSiLo07,
	title = {Application-Specific Topology Design Customization for STNoC},
	booktitle = {DSD07, in proceedings of 10th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD 07)},
	year = {2007},
	month = {August 29-31},
	address = {L{\"u}beck, Germany},
	abstract = {Customized network-oriented communication architectures have recently become a must to support high bandwidth SoCs. To this end, a corresponding communication design flow is necessary to support the design space exploration of complex SoCs with tight design constraints. In order to exploit the benefits introduced by the NoC approach for the on-chip communication, the paper presents a Pareto Simulated Annealing (PSA) approach for the customization of the network topology. The proposed PSA approach has been applied to STNoC, the Network on Chip developed by STMicroelectronics. Starting from the ring topology, the proposed application-specific design flow tries to find a set of customized topologies (optimized in terms of performance and area/energy overhead) by adding custom links up to the spidergon topology.},
	keywords = {application specific design, mapping, network-on-chip (NoC), STNoC, topology customization},
	doi = {http://dx.doi.org/10.1109/DSD.2007.4341522},
	author = {Palermo, Gianluca and Mariani, Giovanni and Silvano, Cristina and Locatelli, Riccardo and Coppola, Marcello}
}
@conference {68.FiPaLuSi07,
	title = {A Data protection Unit for NoC-based Architecture},
	booktitle = {CODES+ISSS 2007, in proceedings of the Fifth IEEE/ACM/FIP International Conference of Hardware/Software Codesign and System Synthesis (CODES+ISSS 2007)},
	year = {2007},
	month = {September 30},
	address = {Salzburg, Austria},
	abstract = {Security is gaining increasing relevance in the development of embedded devices. Towards a secure system at each level of design, this paper addresses the security aspects related to Network-on-Chip (NoC) architectures, foreseen as the communication infrastructure of next generation embedded devices. In the context of NoC-based Multiprocessor systems, we focus on the topic, not thoroughly faced yet, of data protection. We present the architecture of a Data Protection Unit (DPU) designed for implementation within the Network Interface (NI). The DPU supports the capability to check and limit the access rights(none, read, write or both) of processors requesting access to data locations in a shared memory - in particular distinguishing between the operating roles (supervisor or user) of processing elements. We explore different alternative implementations and demonstrate how the DPU unit does not affect the network latency if the memory request has the appropriate rights. In the experimental section we show synthesis results for different ASIC implementations of the Data Protection Unit.},
	keywords = {data protection, embedded systems, multiprocessor system-on-chip (MPSoC), network-on-chip (NoC), security},
	doi = {http://dx.doi.org/10.1145/1289816.1289858},
	author = {Fiorin, Leandro and Palermo, Gianluca and Lukovi{\'c}, Slobodan and Silvano, Cristina}
}
@conference {53.CoReLa07,
	title = {HardwareScheduling Support in SMP Architecture},
	booktitle = {Design, Automation and Test in Europe(DATE)},
	year = {2007},
	month = {April 16-20},
	address = {Nice, France},
	abstract = {In this paper the authors propose a hardware real time operating system (HW-RTOS) that implements the OS layer in a dual-processor SMP architecture. Intertask communication is specified by means of dedicated APIs and the HW-RTOS takes care of the communication requirements of the application and also implements the task scheduling algorithm. The HW-RTOS allows to have smaller footprints, since it avoids the need to link to the final executables traditional software RTOS libraries. Moreover, the HW-RTOS is able to exploit the easy task migration feature provided by an SMP architecture much more efficiently than a traditional software RTOS, due to its faster execution and the authors show how this significantly overcomes the performance achievable with optimal static task partitioning among two processors. Preliminary results show that the hardware overhead in a dual processor architecture is less than 20K gates.},
	keywords = {HW/SW co-design, multiprocessor system-on-chip (MPSoC), real time operating systems},
	doi = {http://dx.doi.org/10.1109/DATE.2007.364666},
	author = {Nacul, Andre Costi and Regazzoni, Francesco and Lajolo, Marcello}
}
@conference {57.PaMaSiLoCo07,
	title = {Mapping and Topology Customization Approaches for Application-Specific STNoC Designs},
	booktitle = {IEEE Proceedings of ASAP{\textquoteright}07 - 18th International Conference on Application-specific Systems, Architectures and Processors},
	year = {2007},
	month = {July},
	address = {Montr{\'e}al, Qu{\'e}bec, Canada},
	abstract = {Application-specific network-oriented communication architectures have recently become an effective solution to support high bandwidth Systems on-Chip. The Network on-Chip architectures considered so far range from regular to fully customized topologies for application specific designs requiring high-level bandwidth. To this end, a networkcentric design flow is necessary to support the design space exploration of complex SoCs with tight design constraints. This paper introduces four different approaches based on the orthogonalization of core mapping and topology customization applied to STNoC, the Network on-Chip developed by STMicroelecronics. The four methods are derived from the combination of the initial mappings to two standard topologies (ring and spidergon) with two types of topology customization based on the insertion of cross-links to reduce the network distance of standard topologies},
	keywords = {application specific design, mapping, network-on-chip (NoC), STNoC, topology customization},
	doi = {http://dx.doi.org/10.1109/ASAP.2007.4429959},
	author = {Palermo, Gianluca and Mariani, Giovanni and Silvano, Cristina and Locatelli, Riccardo and Coppola, Marcello}
}
@conference {73.OtReLa07,
	title = {Rapid Creation of Application Models from Bandwidth Aware Core Graphs},
	booktitle = {Proceedings of: IP Based SoC Design 2007},
	year = {2007},
	month = {December 5-6},
	address = {Grenoble, France},
	abstract = {We present a methodology that allows rapid creation of application models from bandwidth aware core graphs that are available in the literature for a wide range of applications and we discuss their applicability to the rapid exploration of multiple Networks on Chip (NoCs) layout organizations. In a bandwidth aware core graph, each node represents a core and the numbers on the edges represent the bandwidth requirements between cores. We describe core graphs in a UML object model diagram and we then have an automatic code generation tool which produces a SystemC description whose behaviour results in a packet generation on every output connection that respects the bandwidth requirements specified in the core graph. We can then rapidly derive a NoC mapping in which a specific floorplan of the cores can be evaluated and compared with alternate floorplan options for rapid design space exploration.},
	keywords = {network-on-chip (NoC), rapid prototyping},
	author = {Otero, Jo{\~a}o and Regazzoni, Francesco and Lajolo, Marcello}
}
@conference {59.ReBaEi07,
	title = {Simulation-based Methodology for Evaluating DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies},
	booktitle = {International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS IC 07)},
	year = {2007},
	month = {July 16-19},
	address = {Samos, Greece},
	abstract = {This paper explores the resistance of MOS Current Mode Logic (MCML) against Differential Power Analysis (DPA) attacks. Circuits implemented in MCML, in fact, have unique characteristics both in terms of power consumption and the dependency of the power profile from the input signal pattern. Therefore, MCML is suitable to protect cryptographic hardware from DPA and similar side-channel attacks. In order to demonstrate the effectiveness of different logic styles against power analysis attacks, the non-linear bijective function of the Kasumi algorithm (known as substitution box S7) was implemented with CMOS and MCML technology, and a set of attacks was performed using power traces derived from SPICE-level simulations. Although all keys were discovered for CMOS, only very few attacks to MCML were successful.},
	keywords = {current mode logic (CML), differential power analysis (DPA), power simulation, side channel attacks},
	author = {Regazzoni, Francesco and Badel, St{\'e}phane and Eisenbarth, Thomas and Gro{\ss}sch{\"a}dl, Johann and Poschmann, Axel and Toprak, Zeynep and Macchetti, Marco and Pozzi, Laura and Paar, Christof and Leblebici, Yusuf and Ienne, Paolo}
}
@conference {66.PaMaSi07,
	title = {A Topology Design Customization Approach for (STNoC)},
	booktitle = {Nano-Nets 07, in proceedings of 2nd International Conference on Nano-Networks (Nano-Nets 2007).},
	year = {2007},
	month = {September 24-26},
	address = {Catania, Italy},
	abstract = {To support high bandwidth SoCs, a communication design flow is necessary for the design space exploration respecting tight design requirements. In order to exploit the benefits introduced by the NoC approach for the on-chip communication, the paper presents a design flow for the core mapping and customization of the network topology applied to STNoC, the Network on-Chip developed by STMicroelectronics. Starting from ring topology, the proposed application-specific flow tries to find a set of customized topologies, optimized in terms of performance and area/energy overhead, by adding links. The generated STNoC custom topologies provide a reduced cost with respect to the spidergon topology.},
	keywords = {application specific design, mapping, network-on-chip (NoC), STNoC, topology customization},
	doi = {http://dx.doi.org/10.1109/ASAP.2007.4429959},
	author = {Palermo, Gianluca and Mariani, Giovanni and Silvano, Cristina and Locatelli, Riccardo and Coppola, Marcello}
}
@conference {40.1127983,
	title = {Hardware/software partitioning of operating systems: a behavioral synthesis approach},
	booktitle = {GLSVLSI {\textquoteright}06: Proceedings of the 16th ACM Great Lakes symposium on VLSI},
	year = {2006},
	pages = {324{\textendash}329},
	publisher = {ACM Press, New York, USA},
	organization = {ACM Press, New York, USA},
	address = {Philadelphia, PA, USA},
	abstract = {In this paper we propose a hardware real time operating system(HW-RTOS) solution that makes use of a dedicated hardware in order to replace the standard support provided by the POSIX layer of a general purpose RTOS for implementing task synchronization and scheduling. By redefining only the I/O APIs of the tasks, the HW-RTOS then takes care of the communication requirements of the original application and also implements the task scheduling algorithm. The new software application can then be compiled without any need for POSIX support. The main advantages are smaller and faster executables. We present results that show how a small hardware area, less than 10K gates, can result in a 15X performance improvement when the original software scheduler is replaced by a dedicated HW-RTOS.},
	keywords = {HW/SW co-design, real time operating systems, system-on-chip (SoC)},
	isbn = {1-59593-347-6},
	doi = {http://doi.acm.org/10.1145/1127908.1127983},
	author = {Chandra, Satish and Regazzoni, Francesco and Lajolo, Marcello}
}
@conference {36.RegNacLaj2005,
	title = {Automatic Synthesis of the Hardware/Software Interface in Multiprocessor Architectures},
	booktitle = {FDL{\textquoteright}05 - Forum on Specification and Design Languages},
	year = {2005},
	month = {September 27-30},
	address = {Lausanne, Switzerland},
	abstract = {Although Moore{\textquoteright}s Law, in principle, enables a huge number of components to be integrated into a single chip, design methods that will allow system architects to put the components together to achieve cost, power and time-to-market targets are severely lacking. System-level design and optimization techniques can significantly reduce the design gap by providing solutions that achieve correct-by-construction rather than the correct-by-iteration approach. This paper presents a programmatic interface generation tool for automating the generation of the hardware/software interfaces in the context of multiprocessor Systems-On-Chips. The solutions that we present are of crucial importance in a platform based design environment for building a flexible system with reusable IPs and CPU cores.},
	keywords = {HW/SW co-design, system-on-chip (SoC)},
	author = {Regazzoni, Francesco and Nacul, Andre Costi and Lajolo, Marcello}
}
@conference {34.BaLaPrevos2005,
	title = {Design and Synthesis of Reusable Platforms with Programmable Interconnects},
	booktitle = {UML-SoC 2005},
	year = {2005},
	month = {June 12},
	pages = {43-48},
	address = {Anaheim, California},
	abstract = {Platform based design requires to restrict the number of possible design choices in order to make it possible to come up with programmable solutions able to cope with the current complexity of System-On-Chip (SoC) designs. Nowadays there is a general consensus toward the fact that an effective Electronic System Level (ESL) design methodology must provide a specific support for platform specification, hardware/software partitioning and programmatic interfaces synthesis in order to allow designers to exploit the potentials of state-of-the-art technologies. In this work we present a methodology that leverages on UML for building new architectural platforms to be used to be used in the system design process. We show how our methodology can allow to reuse pre-designed platforms by adding new architectural components and by customizing their interconnections},
	keywords = {HW/SW co-design, system-on-chip (SoC), unified modeling language (UML)},
	author = {Basu, Ananda Shankar and Lajolo, Marcello and Prevostini, Mauro}
}
@conference {37.RegLaj2005,
	title = {Hardware/Software Partitioning and Interface Synthesis in Networks On Chip},
	booktitle = {IP Based SoC Design 2005},
	year = {2005},
	month = {December 7-8},
	address = {Grenoble, France},
	abstract = {With deep sub-micron technology, chip designers are expected to create System-On-Chip (SOC) solutions by connecting different Intellectual Property (IP) blocks using efficient and reliable interconnection schemes. On chip networks are quite compelling because, by applying networking techniques to on-chip communication, they allow to implement a fully distributed communication pattern with little or no global coordination. This avoids the problems due to the difficulty of implementing future chips with one single clock source and negligible skew. On the other hand, in order to benefit from the NOC communication paradigm, designers should perform a careful functional mapping for taking advantage of spatial locality, by placing the blocks that communicate more frequently closer together. This reduces the use of long global paths and the corresponding energy dissipation. In this work we show how a tile based NOC architecture can be exploited in order to support a flexible hardware/software partitioning of a system-level specification and we present a methodology for the automatic synthesis of the hardware/software interfaces.},
	keywords = {HW/SW co-design, network-on-chip (NoC), system-on-chip (SoC)},
	author = {Regazzoni, Francesco and Lajolo, Marcello}
}
@inbook {30.BaLaPre2005,
	title = {A Methodology for Bridging the Gap between UML and Codesign},
	booktitle = {UML for SOC Design},
	year = {2005},
	pages = {119-146},
	publisher = {Springer},
	organization = {Springer},
	address = {Dordrecht, The Netherlands},
	abstract = {The Unified Modeling Language (UML) is getting more popular among system designers due to the need to raise the level of abstraction in system specifications. We present here a methodology that integrates UML specifications with a hardware/software codesign platform. This work aims to give a contribution toward SoC Design Automation starting from system level specification down to hardware/software partitioning and integration.},
	keywords = {HW/SW co-design, methodology, system specifications, unified modeling language (UML)},
	author = {Basu, Ananda Shankar and Lajolo, Marcello and Prevostini, Mauro},
	editor = {Martin, Grant and Muller, Wolfgang}
}
@conference {27.RegLaj2004,
	title = {Interface Synthesis in Multiprocessing Systems-on-Chips},
	booktitle = {IP Based SoC Design 2004},
	year = {2004},
	month = {December},
	address = {Grenoble},
	abstract = {Although Moore{\textquoteright}s Law, in principle, enables a huge number of components to be integrated into a single chip, design methods that will allow system architects to put the components together to achieve cost, power and time-to-market targets are severely lacking. System-level design and optimization techniques can significantly reduce the design gap by providing solutions that achieve correct-by-construction approach rather than the correct-by-iteration approach. This paper presents a programmatic interface generation tool for automating the generation of the hardware/software interfaces in the context of multi-processor Systems-On-Chips. The solutions that we present are of crucial importance in a platform based design environment for building a flexible system with reusable IPs and CPU cores.},
	keywords = {HW/SW co-design, system-on-chip (SoC)},
	author = {Regazzoni, Francesco and Lajolo, Marcello}
}
@conference {26.BoFeDuPi2004,
	title = {A Methodology for Testing IPSec-based Systems},
	booktitle = {SoftCOM 2004},
	year = {2004},
	month = {October},
	pages = {22-26},
	address = {Split},
	abstract = {{IPSec is a suite of protocols adding security to communications at the IP level. This suite of protocols is becoming more and more important as it is included as mandatory security mechanism in IPv6. This paper focuses on a methodology for testing IPSec implementations. A UML model of the IPSec suite of protocols was developed. Test cases were obtained applying a coverage method on the same model.}},
	keywords = {encapsulating security payload (ESP), IPSec, security, testing, unified modeling language (UML)},
	author = {Boiko, Uljana and Ferrante, Alberto and Lo Duca, Antonietta and Piuri, Vincenzo}
}
@conference {23.BaLaPre2004,
	title = {UML in an Electronic System Level Design Methodology},
	booktitle = {UML-SOC{\textquoteright}04},
	year = {2004},
	month = {June 6},
	pages = {47-52},
	address = {San Diego, California},
	abstract = {The interest in System-On-Chip (SoC) design using the Unifed Modeling Language (UML) has been growing significantly during the last couple of years. In this paper we would like to present a methodology that aims to address embedded systems design issues at multiple levels of abstraction and to support a function/architecture codesign process. Our approach integrates UML with high-level synthesis and hardware/software co-verification techniques in order to provide an automated flow for SoC design starting from system-level specifications down to hardware/software partitioning and integration. UML has been selected because it is platform independent and helps team members to share very efficiently relevant information during the various design phases, while high-level synthesis helps to evaluate constraints that the embedded system must satisfy: e.g. performance, power and cost starting from behavioral specifications. The paper aims to give a contribution towards SoC Design automation from System-level specification to hardware/software partitioning.},
	keywords = {HW/SW co-design, methodology, system-on-chip (SoC), unified modeling language (UML)},
	author = {Basu, Ananda Shankar and Lajolo, Marcello and Prevostini, Mauro}
}
@conference {24.LaBaPre2004,
	title = {UML Specifications Towards a Codesign Environment},
	booktitle = {FDL{\textquoteright}04},
	year = {2004},
	month = {September 14-17},
	pages = {313-324},
	address = {Lille, France},
	abstract = {The Unified Modeling Language (UML) is receiving more and more attention from system designers that need to model both hardware and software related aspects of a system. On the ground of the growing consensus toward the need to raise the level of abstraction in system specifications, we would like to present a methodology that aims to address embedded systems design issues at multiple levels of abstraction and to support a function/architecture codesign process. Our approach integrates UML with high-level synthesis and hardware/software co-verification techniques in order to provide an automated flow for SoC design starting from system-level specifications down to hardware/software partitioning and integration. UML has been selected because it is platform independent and helps team member to share very efficiently relevant information during the various design phases, while high-level synthesis helps to evaluate constraints that the embedded system must satisfy: e.g. performance, power and cost starting from behavioral specifications.},
	keywords = {embedded systems, HW/SW co-design, system-on-chip (SoC), unified modeling language (UML)},
	author = {Lajolo, Marcello and Basu, Ananda Shankar and Prevostini, Mauro}
}
