@conference {55.DaFeMa,
	title = {A Memory Unit for Priority Management in IPSec Accelerators},
	booktitle = {proceedings of ICC07. Glasgow, Scotland: IEEE Communications Society},
	year = {2007},
	month = {June 24},
	address = {Glasgow, Scotland},
	abstract = {This paper introduces a hardware architecture for high speed network processors, focusing on support for Quality of Service in IPSec-dedicated systems. The effort is aimed at defining a secure system on chip environment, where the speed and security requirements are of utmost importance. In particular, a method is devised to introduce and support Quality of Service through priorities at this level. An architecture of a memory system that provides automatic priority management is proposed.},
	keywords = {accelerator, IPSec, priority, quality of service (QoS), security, system-on-chip (SoC), SystemC},
	doi = {http://dx.doi.org/10.1109/ICC.2007.257},
	author = {Dadda, Luigi and Ferrante, Alberto and Macchetti, Marco}
}
@conference {33.MacDad2005,
	title = {Quasi-Pipelined Hash Circuits},
	booktitle = {IEEE ARITH 17},
	year = {2005},
	month = {June},
	pages = {222-229},
	address = {Cape Cod},
	abstract = {Hash functions are an important cryptographic primitive. They are used to obtain a fixed-size fingerprint, or hash value, of an arbitrary long message. We focus particularly on the class of dedicated hash functions, whose general construction is presented; the peculiar arrangement of sequential and combinational units makes the application of pipelining techniques to these constructions not trivial. We formalize an optimization technique called quasi-pipelining, whose goal is to optimize the critical path and thus to increase the clock frequency in dedicated hardware implementations. The SHA-2 algorithm has been previously examined by Dadda et al, with specific versions of quasi-pipelining; a full generalization of the technique is presented, along with application to the SHA-1 algorithm. Quasi-pipelining could be as well applied to future hashing algorithms, provided they are designed along the same lines as those of the SHA family.},
	doi = {http://dx.doi.org/10.1109/ARITH.2005.36},
	author = {Macchetti, Marco and Dadda, Luigi}
}
@conference {20.989053,
	title = {An ASIC design for a high speed implementation of the hash function SHA-256 (384, 512)},
	booktitle = {GLSVLSI {\textquoteright}04: Proceedings of the 14th ACM Great Lakes symposium on VLSI},
	year = {2004},
	pages = {421{\textendash}425},
	publisher = {ACM Press, New York, USA},
	organization = {ACM Press, New York, USA},
	address = {Boston, MA, USA},
	abstract = {An implementation of the hash functions SHA-256, 384 and 512 is presented, obtaining a high clock rate through a reduction of the critical path length, both in the Expander and in the Compressor of the hash scheme. The critical path is shown to be the smallest achievable. Synthesis results show that the new scheme can reach a clock rate well exceeding 1 GHz using a 0.13?m technology.},
	isbn = {1-58113-853-9},
	doi = {http://doi.acm.org/10.1145/988952.989053},
	author = {Dadda, Luigi and Macchetti, Marco and Owen, Jeff}
}
@conference {18.969266,
	title = {The Design of a High Speed ASIC Unit for the Hash Function SHA-256 (384,512)},
	booktitle = {DATE {\textquoteright}04: Proceedings of the conference on Design, automation and test in Europe},
	year = {2004},
	pages = {30070},
	publisher = {IEEE Computer Society},
	organization = {IEEE Computer Society},
	address = {Washington, DC, USA},
	abstract = {After recalling the basic algorithms published by NIST for implementing the hash functions SHA-256 (384, 512), a basic circuit characterized by a cascade of full adder arrays is given. Implementation options are discussed and two methods for improving speed are exposed: the delay balancing and the pipelining. An application of the former is first given, obtaining a circuit that reduces the length of the critical path by a full adder array. A pipelined version is then given, obtaining a reduction of two full adder arrays in the critical path. The two methods are afterwards combined and the results obtained through hardware synthesis are exposed, where a comparison between the new circuits is also given.},
	isbn = {0-7695-2085-5-3},
	doi = {http://dx.doi.org/10.1109/DATE.2004.1269207},
	author = {Dadda, Luigi and Macchetti, Marco and Owen, Jeff}
}
