Export 46 results:
Author [ Title] Type Year Filters: Author is Cristina Silvano [Clear All Filters]
"Application-Specific Topology Design Customization for STNoC",
DSD07, in proceedings of 10th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD 07), Lübeck, Germany, August 29-31, 2007.
"ARTE: an Application-specific Run-Time Management Framework for Multi-cores based on Queuing Models",
Parallel Computing, 2013.
"ARTE: an Application-specific Run-Time Management Framework for Multi-core Systems",
Proceedings IEEE SASP'11 - Symposium on Application Specific Processors, San Diego, CA, USA, June, 2011.
"A Configurable Monitoring Infrastructure for NoC-Based Architectures",
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. PP, issue 99, 2013.
"A Correlation-based Design Space Exploration Methodology for Multi-Processor Systems-on-Chip",
Proceedings of DAC 2010: Design Automation Conference, Anheim, CA, USA, pp. 120–125, June, 2010.
"A Data protection Unit for NoC-based Architecture",
CODES+ISSS 2007, in proceedings of the Fifth IEEE/ACM/FIP International Conference of Hardware/Software Codesign and System Synthesis (CODES+ISSS 2007), Salzburg, Austria, September 30, 2007.
"Design Space Exploration for Run-Time Management of a Reconfigurable System for Video Streaming",
Multi-objective design space exploration of multiprocessor SoC architectures: the MULTICUBE approach, 1: Springer, pp. 189-204, 2011.
"Design Space Exploration for Run-Time Management of a Reconfigurable System for Video Streaming",
Multi-objective design space exploration of multiprocessor SoC architectures: the MULTICUBE approach, 1: Springer, pp. 189-204, 2011.
"A Design Space Exploration Methodology Supporting Run-Time Resource Management for Multi-Processors System on-Chip",
Proceedings IEEE SASP'09 - Symposium on Application Specific Processors, San Francisco, CA, USA, July, 2009.
"Design Space Exploration of a Reconfigurable System for Supporting Video Streaming Run-time Management",
Multi-objective design space exploration of multiprocessor SoC architectures: the MULTICUBE approach, New York, USA, Springer, 2011.
"Design Space Exploration of Parallel Architectures",
Multi-objective design space exploration of multiprocessor SoC architectures: the MULTICUBE approach, New York, USA, Springer, 2011.
"Design Space Exploration Supporting Run-time Resource Management",
Multi-objective design space exploration of multiprocessor SoC architectures: the MULTICUBE approach, New York, USA, Springer, 2011.
"Design-space Exploration and Runtime Resource Management for Multicores",
ACM Transactions on Embedded Computing Systems (TECS) - Special issue on application-specific processors, vol. 13, issue 2, pp. 20:1–20:27, 09/2013.
"DRuiD: Designing Reconfigurable Architectures with Decision-making Support",
19th Asia and South Pacific Design Automation Conference (ASP-DAC), Singapore, 01/2014.
"An Efficient Design Space Exploration Methodology for Multi-Cluster VLIW Architectures based on Artificial Neural Networks",
Proc. IFIP International Conference on Very Large Scale Integration VLSI - SoC 2008, Rhodes Island, Greece, October 13-15, 2008.
"Energy Estimation and Optimization of Embedded VLIW Processors based on Instruction Clustering",
39th Design Automation Conference, New Orleans, pp. 886-891, June 10-14, 2002.
"Evaluating Run-time Resource Management Policies for Multi-core Embedded Platforms with the EMME Evaluation Framework",
Workshop on Parallel Programming and Run-time Management Techniques for Many-core Architectures, February, 2012.
"An industrial design space exploration framework for supporting run-time resource management on multi-core systems",
Proceedings of Design, Automation and Test in Europe (DATE) Conference, Dresden, Germany, March, 2010.
"An Instruction-Level Methodology for Power Estimation and Optimization of Embedded VLIW cores",
DATE 2002, Paris, pp. 1128, March 4-8, 2002.
"Linking run-time management with design space exploration at multiple abstraction levels",
Proceedings of the DATE'10 workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications, Dresden, Germany, March, 2010.