]
"Run-time Optimization of a Dynamically Reconfigurable Embedded System Through Performance Prediction",
23rd International Conference on Field Programmable Logic and Applications (FPL), Porto, Portugal, IEEE, 09/2013.
"Meta-model Assisted Optimization for Design Space Exploration of Multi-Processor Systems-on-Chip",
Euromicro Proceedings of DSD'09 - Conference on Digital System Design, Patras, Greece, August, 2009.
"Multiprocessor System-on-Chip Design Space Exploration based on Multi-level Modeling Techniques",
Proceedings of IEEE IC-SAMOS'09 - International Conference on Embedded Computer Systems: Architectures, MOdeling, and Simulation, Samos, Greece, July, 2009.
"OSCAR: an Optimization Methodology Exploiting Spatial Correlation in Multi-core Design Space",
IEEE Transactions on Computer-Aided Design, vol. 21, issue 5, no. -: IEEE, pp. 740-753, 05/2012.
"An Efficient Run-Time Management Methodology for Stereo Matching Application",
2PARMA: Proceedings of the Workshop on Parallel Programming and Run-time Management Techniques for Many-core Architectures, Hannover, Germany, February, 2010.
"Cross-layer Design of Reconfigurable Cyber-Physical Systems",
Proceedings of Design, Automation and Test in Europe (DATE) 2017, 2017.
"Fresh Re-Keying: Security against Side-Channel and Fault Attacks for Low-Cost Devices",
Proceedings of Progress in Cryptology - Africacrypt, Stellenbosch, South Africa, May, 2010.
"Fresh Re-Keying II: Securing Multiple Parties against Side-Channel and Fault Attacks",
10th Smart Card Research and Advanced Application Conference (CARDIS), Leuven, Belgium, September, 2011.
"System Adaptivity and Fault-tolerance in NoC-based MPSoCs: the MADNESS Project Approach",
Proceedings of the 15th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD'12), Izmir, Turkey, September 5-8, 2012.
Reconfigurable Logic Circuit,
, no. GB1719355.8, 11/2017, Submitted.
"Rethinking Secure FPGAs: TowardsCryptography-friendly Configurable Cell Architecture and its Automated Design Flow",
Proceedings of FCCM, 05/2018.
"NPART - node placement algorithm for realistic topologies in wireless multihop network simulation",
Proceedings of the 2nd International Conference on Simulation Tools and Techniques, ICST, Brussels, Belgium, Belgium, ICST (Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering), 2009.
"Runtime Classification of Mobile Malware for Resource-constrained Devices",
Lecture Notes in Communications in Computer and Information Science, vol. 764: Springer International Publishing AG, pp. 195-215, 2017.
"A Resource-optimized Approach to Efficient Early Detection of Mobile Malware",
3rd International Workshop on Security of Mobile Applications - IWSMA 2014, Fribourg, Switzerland, 09/2014.
"A General Practitioner or a Specialist for Your Infected Smartphone?",
36th IEEE Symposium on Security and Privacy , San Jose, CA, USA, IEEE Computer Society Technical Committee on Security and Privacy, 05/2015.
"Trojan Families Identification Using Dynamic Features and Low Complexity Classifiers",
24th EICAR Annual Conference 2016 "Trustworthiness in IT Security Products", Nuremberg, Germany, EICAR, 10/2016.
"Malware Threats and Solutions for Trustworthy Mobile Systems Design",
Hardware Security and Trust: Design and Deployment of Integrated Circuits in a Threatened Environment, First edition; 2016: Springer, pp. 149-167, 2017.
"A Friend or a Foe? Detecting Malware Using Memory and CPU Features",
SECRYPT 2016, 13th International Conference on Security and Cryptography, Lisbon, Portugal, SciTePress Digital Library, 07/2016.
"Security Challenges for Hardware Designers of Mobile Systems",
2015 Mobile Systems Technologies Workshop (MST), May, 2015.
"Risk Assessment of Atrial Fibrillation: a Failure Prediction Approach",
41st Computing in Cardiology Conference (CinC), Cambridge, MA, USA, IEEE Computer Society, 09/2014.