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Filters: Author is Gianluca Palermo [Clear All Filters]
"Mapping and Topology Customization Approaches for Application-Specific STNoC Designs", IEEE Proceedings of ASAP'07 - 18th International Conference on Application-specific Systems, Architectures and Processors, Montréal, Québec, Canada, July, 2007.
"Meta-model Assisted Optimization for Design Space Exploration of Multi-Processor Systems-on-Chip", Euromicro Proceedings of DSD'09 - Conference on Digital System Design, Patras, Greece, August, 2009.
"A Monitoring System for NoCs", Proceedings of the Third International Workshop on Network on Chip Architectures (NoCArc'2010), Atlanta, Georgia, USA, December, 2010.
"MPSoCs Run-Time Monitoring through Networks-on-Chip", The 2009 Conference on Design, Automation and Test In Europe (DATE'09), Nice, France, April/2009.
"Multicube Explorer - A Design Space Exploration Framework for Embedded Systems-on-Chip", Proceedings of the DATE'09 workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications, Nice, France, April, 2009.
"Multicube Explorer: An Open Source Framework for Design Space Exploration of Chip Multi-Processors", 2PARMA: Proceedings of the Workshop on Parallel Programming and Run-time Management Techniques for Many-core Architectures, Hannover, Germany, February, 2010.
"Multicube: Multi-objective design space exploration of multi-core architectures", ISVLSI 2010: IEEE Annual Symposium on VLSI, Lixouri, Kefalonia - Greece, pp. 488–493, July, 2010.
"MULTICUBE: Multi-Objective Design Space Exploration of Multiprocessor Architectures for Embedded Multimedia Applications", Proceedings of the DATE'09 workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications, Nice, France, April, 2009.
"Multiprocessor System-on-Chip Design Space Exploration based on Multi-level Modeling Techniques", Proceedings of IEEE IC-SAMOS'09 - International Conference on Embedded Computer Systems: Architectures, MOdeling, and Simulation, Samos, Greece, July, 2009.
"A Reconfigurable Multiprocessor Architecture for a Reliable Face Recognition Implementation", Proceedings of Design, Automation and Test in Europe (DATE) Conference, Dresden, Germany, March, 2010.
"Run-time Optimization of a Dynamically Reconfigurable Embedded System Through Performance Prediction", 23rd International Conference on Field Programmable Logic and Applications (FPL), Porto, Portugal, IEEE, 09/2013.
"A Security Monitoring Service for NoCs", Sixth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'08), Atlanta, Georgia, USA., 10/2008.
"A Topology Design Customization Approach for (STNoC)", Nano-Nets 07, in proceedings of 2nd International Conference on Nano-Networks (Nano-Nets 2007)., Catania, Italy, September 24-26, 2007.
"Using Multi-objective Design Space Exploration to Enable Run-time Resource Management for Reconfigurable Architectures", Proc. Design, Automation Test in Europe Conf. Exhibition (DATE), March, 2012.
"Yield Enhancement by Robust Application-specific Mapping on Network-on-Chips", NoCArc'09: Proceedings of the Second International Workshop on Network on-Chip Architectures, New York City, USA, pp. 37–42, December, 2009.
"ARTE: an Application-specific Run-Time Management Framework for Multi-cores based on Queuing Models", Parallel Computing, 2013.
"A Configurable Monitoring Infrastructure for NoC-Based Architectures", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. PP, issue 99, 2013.
"Design-space Exploration and Runtime Resource Management for Multicores", ACM Transactions on Embedded Computing Systems (TECS) - Special issue on application-specific processors, vol. 13, issue 2, pp. 20:1–20:27, 09/2013.
"Linking run-time resource management of embedded multi-core platforms with automated design-time exploration", IET Computers and Digital Techniques, vol. 5, no. -, pp. 123–135, 2011.
"OSCAR: an Optimization Methodology Exploiting Spatial Correlation in Multi-core Design Space", IEEE Transactions on Computer-Aided Design, vol. 21, issue 5, no. -: IEEE, pp. 740-753, 05/2012.