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"Bridging the Gap between Software and Hardware Designers Using High-Level Synthesis", Advances in Parallel Computing, 2018.
"DarkMem: Fine-Grained Power Management of Local Memories for Accelerators in Embedded Systems", Proceedings of the Asia and South Pacific Design Automation Conference (ASPDAC), 2018.
"High-Level Synthesis of Benevolent Trojans", Proceedings of the IEEE Design, Automation and Test in Europe Conference (DATE), 2019.
"TAO: Techniques for Algorithmic Obscuration during High-Level Synthesis", Proceedings of the ACM/IEEE Design Automation Conference (DAC), 2018.
"Black-Hat High-Level Synthesis: Myth or Reality?", IEEE Transactions on Very Large Scale Integration Systems, In Press.
"The Case for Polymorphic Registers in Dataflow Computing", International Journal of Parallel Programming, vol. 54, issue 5, pp. 54-62, 10/2018.
"Enabling Automated Bug Detection for IP-based Designs using High-Level Synthesis", IEEE Design & Test, 2018, In Press.
"Securing Hardware Accelerators: a New Challenge for High-Level Synthesis", IEEE Embedded Systems Letters, vol. 3, issue 10, pp. 77-80, 11/2017, 2018.
"System-Level Optimization of Accelerator Local Memory for Heterogeneous Systems-on-Chip", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 36, pp. 435-448, 2017.
"TaintHLS: High-Level Synthesis For Dynamic Information Flow Tracking", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, In Press.