@inbook {18571,
	title = {Fault Attacks, Injection Techniques and Tools for Simulation},
	booktitle = {Hardware Security and Trust: Design and Deployment of Integrated Circuits in a Threatened Environment},
	year = {2017},
	pages = {149-167},
	publisher = {Springer},
	organization = {Springer},
	edition = {First edition; 2016},
	author = {Piscitelli, Roberta and Bhasin, Shivam and Regazzoni, Francesco}
}
@article {18455,
	title = {A Framework for Disturbance Analysis in Smart Grids by Fault Injection},
	journal = {Springer Journal on "Computer Science - Research and Development"},
	year = {2016},
	month = {09/2016},
	abstract = {With growing complexity of electric power systems, a total number of disturbances is expected to increase. Analyzing these disturbances and understanding grid{\textquoteright}s behavior, when under a disturbance, is a pre-requisite for designing methods for boosting grid{\textquoteright}s stability. The main obstacle to the analysis is a lack of relevant data that are publicly available. In this paper, we design and implement a framework for emulation of grid disturbances by employing simula-tion and fault-injection techniques. We also present a case study on generating voltage sag related data. A foreseen usage of the framework considers mainly prototyping, root-cause analysis and design and comparison of methods for disturbance detection and prediction. },
	issn = {1865-2042},
	doi = {10.1007/s00450-016-0313-8},
	url = {http://dx.doi.org/10.1007/s00450-016-0313-8},
	author = {Kaitovi{\'c}, Igor and Obradovi{\'c}, Filip and Lukovi{\'c}, Slobodan and Malek, Miroslaw}
}
@conference {18459,
	title = {A Friend or a Foe? Detecting Malware Using Memory and CPU Features},
	booktitle = {SECRYPT 2016, 13th International Conference on Security and Cryptography},
	year = {2016},
	month = {07/2016},
	publisher = {SciTePress Digital Library},
	organization = {SciTePress Digital Library},
	address = {Lisbon, Portugal},
	author = {Milosevic, Jelena and Malek, Miroslaw and Ferrante, Alberto}
}
@conference {18480,
	title = {Fault attacks, injection techniques and tools for simulation},
	booktitle = {10th International Conference on Design Technology of Integrated Systems in Nanoscale Era DTIS 2015},
	year = {2015},
	month = {04/2015},
	pages = {1-6},
	publisher = {IEEE},
	organization = {IEEE},
	address = {Naples, Italy},
	abstract = {Faults attacks are a serious threat to secure devices, because they are powerful and they can be performed with extremely cheap equipment. Resistance against fault attacks is often evaluated directly on the manufactured devices, as commercial tools supporting fault evaluation do not usually provide the level of details needed to assert the security of a device. Early identification of weak points would instead be very useful as it would allow to immediately apply the appropriate countermeasures directly at design time. Moving towards this goal, in this work, we survey existing fault attacks and techniques for injecting faults, and we analyze the suitability of existing electronic design automaton commodities for estimating resistance against fault attacks. Our exploration, which includes the type of attacks that can be simulated and the limitations of each considered simulation approach, is an initial step towards the development of a complete framework for asserting fault attack robustness},
	keywords = {fault attacks robustness, fault resilience, injection techniques, secure devices, security, security of data},
	isbn = {978-1-4799-1999-4},
	doi = {10.1109/DTIS.2015.7127352},
	url = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=7118811},
	author = {Piscitelli, Roberta and Bhasin, Shivam and Regazzoni, Francesco}
}
@article {18049,
	title = {Fault-Tolerant Network Interfaces for Networks-on-Chip},
	journal = {IEEE Trans. Dependable Secur. Comput.},
	volume = {11},
	issue = {1},
	year = {2014},
	month = {01/2014},
	pages = {16{\textendash}29},
	keywords = {fault tolerance, high-level error models, network interface, Networks-on-chip, online fault detection, reliability},
	issn = {1545-5971},
	doi = {10.1109/TDSC.2013.28},
	author = {Fiorin, Leandro and Sami, Mariagiovanna}
}
@article {18061,
	title = {A Fast ULV Logic Synthesis Flow in Many-Vt CMOS Processes for Minimum Energy under Timing Constraints},
	journal = {IEEE Transactions on Circuits and Systems II},
	volume = {59},
	issue = {12},
	year = {2013},
	pages = {947-951},
	abstract = {Ultra-low-voltage (ULV) logic offers the opportunity to operate at the minimum-energy point (MEP) for applications with low-to-medium speed requirements. Unfortunately, the critical design constraint of achieving a reliable timing closure at the target frequency of the application becomes very complex in the wide design space of ULV including supply (Vdd) and threshold (Vt) voltage selection as well as netlist optimizations from the synthesis. In this paper, we propose a fast synthesis flow to accurately predict the Vdd/Vt MEP under strict timing constraints. Compared to an exhaustive search for the MEP under timing constraints based on numerous library recharacterizations and synthesis steps for all Vdd/Vt pairs, the proposed ULV flow dramatically speeds up the design process. Indeed, it requires a single library recharacterization and only three synthesis steps. Results obtained for several ITC{\textquoteright}99 benchmarks under a wide range of timing constraints from 0.1 to 30 MHz in 65-nm LP/GP CMOS demonstrate that the proposed flow has a less than 10\% energy penalty with respect to the absolute MEP computed with an exhaustive search and energy savings enhanced up to 2.4{\texttimes} compared to a conventional flow with Vdd scaling only.},
	issn = {1549-7747},
	doi = {10.1109/TCSII.2012.2231034},
	author = {Bol, David and Hocquet, C{\'e}dric and Regazzoni, Francesco}
}
@article {18491,
	title = {A Fast ULV Logic Synthesis Flow in Many-Vt CMOS Processes for Minimum Energy Under Timing Constraints},
	journal = {IEEE Transactions on Circuits and Systems II: Express Briefs  },
	volume = {59-II},
	issue = {12},
	year = {2012},
	month = {02/2012},
	pages = {947-951},
	type = {journal},
	chapter = {947},
	abstract = {Ultra-low-voltage (ULV) logic offers the opportunity to operate at the minimum-energy point (MEP) for applications with low-to-medium speed requirements. Unfortunately, the critical design constraint of achieving a reliable timing closure at the target frequency of the application becomes very complex in the wide design space of ULV including supply (Vdd) and threshold (Vt) voltage selection as well as netlist optimizations from the synthesis. In this paper, we propose a fast synthesis flow to accurately predict the Vdd/Vt MEP under strict timing constraints. Compared to an exhaustive search for the MEP under timing constraints based on numerous library recharacterizations and synthesis steps for all Vdd/Vt pairs, the proposed ULV flow dramatically speeds up the design process. Indeed, it requires a single library recharacterization and only three synthesis steps. Results obtained for several ITC{\textquoteright}99 benchmarks under a wide range of timing constraints from 0.1 to 30 MHz in 65-nm LP/GP CMOS demonstrate that the proposed flow has a less than 10\% energy penalty with respect to the absolute MEP computed with an exhaustive search and energy savings enhanced up to 2.4{\texttimes} compared to a conventional flow with Vdd scaling only},
	keywords = {circuit optimisation, CMOS logic circuits, fast ULV logic synthesis flow, Low power electronics},
	issn = {1549-7747},
	doi = {10.1109/TCSII.2012.2231034},
	url = {http://dx.doi.org/10.1109/TCSII.2012.2231034},
	author = {Bol, David and Hocquet, C{\'e}dric and Regazzoni, Francesco}
}
@conference {18080,
	title = {A First Step Towards Automatic Application of Power Analysis Countermeasures},
	booktitle = {48th Design Automation Conference (DAC)},
	year = {2011},
	month = {June},
	address = {San Diego, Califorina},
	author = {Bayrak, Ali Galip and Regazzoni, Francesco and Brisk, Philip and Standaert, Fran{\c c}ois-Xavier and Ienne, Paolo}
}
@conference {18086,
	title = {FPGA Implementations of the AES Masked Against Power Analysis Attacks},
	booktitle = {2nd International Workshop on Constructive Side-Channel Analysis and Secure Design (COSADE)},
	year = {2011},
	month = {February},
	address = {Darmstadt, Germany},
	author = {Regazzoni, Francesco and Yi, Wang and Standaert, Fran{\c c}ois-Xavier}
}
@conference {17696,
	title = {A Framework for Security and Workload Gradual Adaptation},
	booktitle = {SECRYPT},
	year = {2011},
	month = {07/2011},
	publisher = {ICETE},
	organization = {ICETE},
	address = {Seville, Spain},
	author = {Taddeo, Antonio Vincenzo and Morales, Luis Germ{\'a}n Garcia and Ferrante, Alberto}
}
@conference {18077,
	title = {Fresh Re-Keying II: Securing Multiple Parties against Side-Channel and Fault Attacks},
	booktitle = {10th Smart Card Research and Advanced Application Conference (CARDIS)},
	year = {2011},
	month = {September},
	address = {Leuven, Belgium},
	author = {Medwed, Marcel and Petit, Christophe and Regazzoni, Francesco and Renauld, Mathieu and Standaert, Fran{\c c}ois-Xavier}
}
@conference {18083,
	title = {Fresh Re-Keying: Security against Side-Channel and Fault Attacks for Low-Cost Devices},
	booktitle = {Proceedings of Progress in Cryptology - Africacrypt},
	year = {2010},
	month = {May},
	address = {Stellenbosch, South Africa},
	author = {Medwed, Marcel and Standaert, Fran{\c c}ois-Xavier and Gro{\ss}sch{\"a}dl, Johann and Regazzoni, Francesco}
}
@conference {130.LuKaMuBoKuPo10,
	title = {Functional model of Virtual Power Plant (VPP)},
	booktitle = {Proceedings of the 2010 CIGRE (International Council on Large Electric Systems) Session},
	year = {2010},
	month = {July},
	address = {Paris, France},
	keywords = {smart grid, unified modeling language (UML), virtual power plants},
	author = {Lukovi{\'c}, Slobodan and Kaitovi{\'c}, Igor and Mura, Marcello and Bondi, Umberto and Kuli{\'c}, Filip and Popovi{\'c}, Dragan}
}
@conference {102.LuKaMuBo09,
	title = {Functional requirements of embedded systems for monitoring and control structure of Virtual Power Plants},
	booktitle = {Proceedings of the 2009 IEEE Workshop on Environmental, Energy, and Structural Monitoring Systems},
	year = {2009},
	month = {September},
	address = {Crema, Italy},
	abstract = {Efficient integration of distributed renewable generation into a reliable single entity in technical and commercial terms is one of key issues for successful realization of smart-grids. The novel concept of Virtual Power Plants (VPP) emerges to be promising response to these needs. ICT is the enabling technology for VPP implementation. In fact, an efficient monitoring and control system coupled with appropriate communication structure must be designed in a scalable and modular way so that full interoperability among components of the system is achieved. On top of that, Control Center applications take care of power flow optimization (production, consumption, ancillary services) and high-level applications (e.g. energy trading, Demand Side Management etc.). In this work we focus on functional requirements for realization of such concept by means of embedded systems.},
	keywords = {monitoring and control, system level modeling, virtual power plants},
	doi = {http://dx.doi.org/10.1109/EESMS.2009.5341320},
	author = {Lukovi{\'c}, Slobodan and Kaitovi{\'c}, Igor and Mura, Marcello and Bondi, Umberto}
}
@conference {31.1070384,
	title = {Flexible Power Modeling for Wireless Systems: Power Modeling and Optimization of two Bluetooth Implementations},
	booktitle = {WOWMOM {\textquoteright}05: Proceedings of the Sixth IEEE International Symposium on a World of Wireless Mobile and Multimedia Networks (WoWMoM{\textquoteright}05)},
	year = {2005},
	pages = {408{\textendash}416},
	publisher = {IEEE Computer Society},
	organization = {IEEE Computer Society},
	address = {Washington, DC, USA},
	abstract = {A large number of embedded multimedia applications are characterized by high instruction-level parallelism (ILP) expecially in the most critical internal loop bodies. Very Large Instruction Word (VLIW) architectures Application Specific Instruction Set Processors (ASIP) are best suited to exploit such parallelism. Fast design space exploration and optimization of VLIW architecture to a specific application target is increasingly becoming the crucial factor to achieve higher efficiency designs in a relatively small amount of time. In this paper we propose an example of VLIW architecture application driven optimization using the VEX (VLIW Example) system. A typical image processing application, the Imaging Pipeline, has been chosen as an example.},
	isbn = {0-7695-2342-0-01},
	doi = {http://dx.doi.org/10.1109/WOWMOM.2005.46},
	author = {Negri, Luca and Sami, Mariagiovanna and Tran, Que Dung and Zanetti, Davide}
}
@conference {32.Salvioni2005,
	title = {From a young academic institute a broad minded approach: the working and learning environment of the ALaRI Intranet tool (case study)},
	booktitle = {MICROLEARNING 2005: Learning \& Working in New Media Environments},
	year = {2005},
	month = {June 23-24},
	address = {Innsbruck, Austria},
	abstract = {The aim of this paper is to present an innovative approach to the working organization and learning environment, experimented at ALaRI (Advanced Learning and Research Institute), the academic institute at the Universit{\`a} della Svizzera italiana, in Switzerland, that, since 1999, promotes research and education in embedded systems design . Through the introduction and the use of an ad-hoc intranet tool, new social and technological dynamics have been developing at the institute, integrating learning in presence with remote cooperation in a complex and distributed reality. Presenting the practical experiences occurred within the ALaRI environment, through an analysis of the context needs and of the tool usability, the reader will discover the conditions and the reasons that have led to designing and implementing this intranet platform, but also troubles and limitations of the intranet will be explored from a usability and communication point of view. From these experiences a plentiful research material arises to investigate new workflows and new ideas for virtual workplace.},
	keywords = {case study, remote cooperation, virtual workplace, workplace studies},
	author = {Salvioni, Carola}
}
@conference {16.1013323,
	title = {FSM{\textendash}based power modeling of wireless protocols: the case of bluetooth},
	booktitle = {ISLPED {\textquoteright}04: Proceedings of the 2004 international symposium on Low power electronics and design},
	year = {2004},
	pages = {369-374},
	publisher = {ACM Press, New York, USA},
	organization = {ACM Press, New York, USA},
	address = {Newport Beach, California, USA},
	abstract = {The proliferation of pervasive computing applications relying on battery-powered devices and wireless connectivity is posing great emphasis on the issue of power optimization. While node-level models and approaches have been widely discussed, a problem requiring even greater attention is that of power associated with the communication protocols. We propose a high-level modeling methodology based on Finite State Machines useful to predict the energy consumption of given communication tasks with very low computational cost, which can be applied to any protocol. We use this methodology to create a power model of Bluetooth that we characterize and validate experimentally on a real implementation.},
	keywords = {bluetooth, power modeling, wireless protocols},
	isbn = {1-58113-929-2},
	doi = {http://dx.doi.org/10.1109/LPE.2004.1349368},
	author = {Negri, Luca and Sami, Mariagiovanna and Macii, David and Terranegra, Alessandra}
}
