@conference {18464,
	title = {Embedded Systems Education: Job Market Expectations},
	booktitle = {Workshop on Embedded and Cyber-Physical Systems Education (WESE) },
	year = {2014},
	month = {10/2014},
	publisher = {ACM},
	organization = {ACM},
	address = {New Delhi, India},
	abstract = {In the fifteen years since the first Embedded Systems Design Master studies were proposed the embedded systems world has radically changed. The spectrum of application areas has increased beyond any expectation, and the increasing presence of embedded systems in the physical world has led to "cyber-physical systems." Devices tend to become a commodity in many cases, while sensors and IPs acquire a larger share of the market. The whole industrial ecosystem is changing as well, with "application" companies becoming increasingly present and SMEs emerging as major players. It becomes mandatory to reconsider the competences and capacities that should be provided in a Master of Science course oriented to Embedded Systems Design, so as to meet new and diverse requests that come from job market and prospective employers. Within the frame of the Nano-Tera Swiss Federal program (www.nano-tera.ch), the educational project Future Embedded Systems Education (FESTE) aimed at identifying requests coming from the job market, so as to outline the renewed professional profile for young Embedded Systems Designers. The results indicate that programming, networking, real time and system architecture know-how combined with soft skills such as teamwork and communication are in demand and frequently come under disguised names such as automation or control engineering.},
	keywords = {Cyber-Physical Systems Education, embedded systems, Nano Tera program},
	isbn = {978-1-4503-3090-9},
	url = {http://doi.acm.org/10.1145/2829957.2829961},
	author = {Sami, Mariagiovanna and Malek, Miroslaw and Bondi, Umberto and Regazzoni, Francesco}
}
@article {18049,
	title = {Fault-Tolerant Network Interfaces for Networks-on-Chip},
	journal = {IEEE Trans. Dependable Secur. Comput.},
	volume = {11},
	issue = {1},
	year = {2014},
	month = {01/2014},
	pages = {16{\textendash}29},
	keywords = {fault tolerance, high-level error models, network interface, Networks-on-chip, online fault detection, reliability},
	issn = {1545-5971},
	doi = {10.1109/TDSC.2013.28},
	author = {Fiorin, Leandro and Sami, Mariagiovanna}
}
@article {18050,
	title = {A system-level approach to adaptivity and fault-tolerance in NoC-based MPSoCs: The MADNESS project.},
	journal = {Microprocessors and Microsystems - Embedded Hardware Design},
	volume = {37},
	issue = {6-7},
	year = {2013},
	pages = {515{\textendash}529},
	doi = {10.1016/j.micpro.2013.07.007},
	author = {Derin, Onur and Cannella, Emanuele and Tuveri, Giuseppe and Meloni, Paolo and Stefanov, Todor and Fiorin, Leandro and Raffo, Luigi and Sami, Mariagiovanna}
}
@conference {17737,
	title = {System Adaptivity and Fault-tolerance in NoC-based MPSoCs: the MADNESS Project Approach},
	booktitle = {Proceedings of the 15th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD{\textquoteright}12)},
	year = {2012},
	month = {September 5-8},
	address = {Izmir, Turkey},
	abstract = {Modern embedded systems increasingly require adaptive run-time management. The system may adapt the mapping of the applications in order to accommodate the current workload conditions, to balance load for efficient resource utilization, to meet quality of service agreements, to avoid thermal hot-spots and to reduce power consumption. As the possibility of experiencing run-time faults becomes increasingly relevant with deep-sub-micron technology nodes, in the scope of the MADNESS project, we focus particularly on the problem of graceful degradation by dynamic remapping in presence of run-time faults. In this paper, we summarize the major results achieved in the MADNESS project until now regarding the system adaptivity and fault tolerant processing. We report the first results of the integration between platform level and middleware level support for adaptivity and fault tolerance. A case study demonstrates the survival ability of the platform via a low-overhead process migration mechanism and a near-optimal online remapping heuristic.},
	keywords = {fault tolerance, kahn process networks (KPN), middleware, network-on-chip (NoC), process migration, system adaptivity},
	doi = {http://dx.doi.org/10.1109/DSD.2012.122},
	author = {Meloni, Paolo and Tuveri, Giuseppe and Raffo, Luigi and Cannella, Emanuele and Stefanov, Todor and Derin, Onur and Fiorin, Leandro and Sami, Mariagiovanna}
}
@conference {18493,
	title = {ADSC: Application-Driven Storage Control for Energy Efficiency},
	booktitle = {Information and Communication on Technology for the Fight against Global Warming - First International Conference ICT-GLOW},
	series = {Lecture Notes in Computer Science },
	volume = {6868},
	year = {2011},
	month = {08/2011},
	pages = {165-179},
	publisher = {Springer},
	organization = {Springer},
	address = {Toulouse, France},
	abstract = {While performance and quality of service are the main criteria for application data management on storage units, energy efficiency is increasingly being stated as an additional criterion for evaluation. Due to the increasing energy consumption of storage subsystems, improving their energy efficiency is an important issue. In this paper we present a novel approach to storage management whereby both mid-level (file placement) and low level (disk mode) aspects are controlled, in a tiered storage architecture. The proposed mechanism is based on policies, and it is implemented via fuzzy logic rules, in contrast to attempting to build a model of the storage subsystem. The inputs to the storage management system are high level (application), mid level (file system) and low level (disk access patterns) information. The effectiveness of our approach has been validated by means of a case study using a TPC-C benchmark modified to access file level data. Results from this simulation are presented.},
	isbn = {978-3-642-23446-0},
	doi = {10.1007/978-3-642-23447-7_15},
	url = {http://dx.doi.org/10.1007/978-3-642-23447-7_15},
	author = {Cappiello, Cinzia and Hinostroza, Alicia and Pernici, Barbara and Sami, Mariagiovanna and Henis, Ealan and Kat, Ronen I. and Meth, Kalman Z. and Mura, Marcello}
}
@conference {151.FiMiSa11,
	title = {Design of Fault Tolerant Network Interfaces for NoCs},
	booktitle = {Proceedings of 14th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD{\textquoteright}11)},
	year = {2011},
	month = {September},
	address = {Oulu, Finland},
	keywords = {fault tolerance, network interface, network-on-chip (NoC), system-on-chip (SoC)},
	doi = {http://dx.doi.org/10.1109/DSD.2011.54},
	author = {Fiorin, Leandro and Micconi, Laura and Sami, Mariagiovanna}
}
@inbook {160.MuSaLuMa.2011,
	title = {Progettazione e valutazione di soluzioni wireless multi-hop per il monitoraggio ambientale},
	booktitle = {MIARIA: Techologia e Conoscenza al Servizio della Sicurezza},
	year = {2011},
	pages = {108-120},
	publisher = {Bellavite},
	organization = {Bellavite},
	address = {Missaglia, Italy},
	abstract = {The creation of a sensors network for environmental monitoring, taking into account the functional and non-functional requirements, poses a series of problems that must be dealt with during the design phase. The main difficulties are related to the power of the nodes and their location so that the resulting network topology minimizes the overall energy consumption while guaranteeing the desired measurement accuracy. The adoption of a {\textquoteright}wireless{\textquoteright} communication model allows for greater flexibility during installation and allows creating remote connections more easily than the traditional wired pattern. Extension of the network topology by add ing new devices in the monitoring area or movement of devices already deployed are greatly simplified. But the requirements in terms of fault-tolerance and power consumption of a wireless network are in general more difficult to meet. In this chapter we propose two different solutions that improve performance in terms of power consumption of the main standard for communication in wireless sensor networks field (e.g. ZigBee) customizing it for monitoring applications in an open environment on geographical areas of several hectares. While the standard is intended to be as general as possible, optimizations have been included considering the special needs of our monitoring applications, in terms of number of nodes, topology density, nodes duty cycle and data-load. The first solution deals with the management of multi-hop communication and allows the use of devices that can be powered by batteries (and possibly small solar panels) for the relaying nodes. The second solution optimizes the management of faults (transient or permanent) in the network topology. It is rarely possible to develop and evaluate proposed solutions in the field prior to actual deployment, therefore simulation is an essential step in developing solutions for these applications. The simulation must be accurate and must provide an analysis of all issues related to communication and the behavioural dynamics of the single node in the network structure. For this reason the evaluation has been carried out by means of a modelling methodology developed expressly for wireless sensor networks.},
	isbn = {978-88-7511-164-9},
	author = {Mura, Marcello and Sami, Mariagiovanna and Luppi, Alessandro and Malchiodi, Gianluca}
}
@conference {106.BoSa09,
	title = {Creating an Embedded Systems Program from Scratch: Nine years of experience at ALaRI},
	booktitle = {Proceedings of the 2009 Workshop on Embedded System Education},
	year = {2009},
	month = {October},
	address = {Grenoble, France},
	abstract = {In 1999, experts form academia and industry met in a workshop dealing with education in Embedded Systems Design: at the time there were no specifically oriented programs, and an {\textquoteright}ideal{\textquoteright} educational track was designed. One year later, that educational design was implemented with a one-year {\textquoteright}executive-type{\textquoteright} Master at Universit{\`a} della Svizzera italiana, in Switzerland; over the years, the program blossomed and extended, with development of a two-year Master of Science program as well. The experience is discussed here; results and perspectives are analyzed.},
	keywords = {education, embedded systems},
	doi = {http://dx.doi.org/10.1145/1719010.1719012},
	author = {Bondi, Umberto and Sami, Mariagiovanna}
}
@conference {85.MuSaParma08,
	title = {Code Generation from Statecharts: Simulation of Wireless Sensor Networks},
	booktitle = {Proceedings of DSD08},
	year = {2008},
	month = {September},
	address = {Parma, Italy},
	abstract = {Automatic generation of code starting from lightweight modeling languages such as UML is by now a widely adopted approach. In particular generation of executable SystemC models starting from StateCharts and other UML diagrams represents a promising research field. While RTL SystemC appears better suited for matching the StateCharts formalism (being intrinsically clocked), performances of the generated code suffer from the heavy overhead induced by time management, specially when the number of concurrent processes is high. In this paper we present a methodology that allows applying a solution mixing event based and clock-driven approach. More specifically, clock-driven simulation is activated only when the configuration of the system is identified to be evolving. When no events are present this fact is also detected (together with the interval of absence of events) so that no simulation is performed although the clock runs on. This solution is particularly suited for low duty cycle systems, as, e.g. when simulating Wireless Sensor Networks (WSN); in such instances, speedup of the generated code has been found to be well over two orders of magnitude. Application of the technique to the generation of a power simulator for the IEEE 802.15.4 networking protocol is used as a test case.},
	keywords = {low power design, modeling, protocol, wireless sensor networks},
	doi = {http://dx.doi.org/10.1109/DSD.2008.106},
	author = {Mura, Marcello and Sami, Mariagiovanna}
}
@conference {79.Ptsbrg,
	title = {Modelling the Power Cost of Security in Wireless Sensor Networks : the Case of 802.15.4},
	booktitle = {Proceedings of IEEE ICT08},
	year = {2008},
	month = {June},
	address = {Saint Petersburg, Russia},
	abstract = {Pervasive applications and in particular Wireless Sensors Networks have very strict requirements in terms of power consumption. It is well known that radio activity is very expensive in terms of energy; we show here that intensive processing activities (as security) represent a major contribution to power budget. In this paper we extend our methodology for analyzing the impact of Security related operations on power consumption and optimizing it. The analysis is based on experimental data and was validated with measurements on a real platform.},
	keywords = {low power design, modeling, protocol, wireless sensor networks},
	doi = {http://dx.doi.org/10.1109/ICTEL.2008.4652616},
	author = {Mura, Marcello and Fabbri, Fabio and Sami, Mariagiovanna}
}
@conference {49.MuPaNeSaFa07,
	title = {Power Modeling and Power Analysis for IEEE 802.15.4: a Concurrent State Machine Approach},
	booktitle = {Proceedings of CCNC 2007},
	year = {2007},
	month = {January 11-13},
	address = {Las Vegas, USA},
	abstract = {802.15.4 is a recent low-rate/low-power standard for wireless personal area and sensor networks. Its simple infrastructure, intermediate range and good power performance make it a candidate for applications that require a reasonably low throughput but a very high device lifetime and power efficiency. An experimental power analysis of an 802.15.4 implementation is carried out, providing a detailed power model of the protocol based on concurrent state machines; resulting power model is then used to generate a customized simulator. The model has been validated through a set of experiments and provides good accuracy; results are discussed, considering in particular use of the model as a basis for subsequent optimizations on 802.15.4 networks.},
	keywords = {low power design, modeling, wireless sensor networks},
	doi = {http://dx.doi.org/10.1109/CCNC.2007.135},
	author = {Mura, Marcello and Paolieri, Marco and Negri, Luca and Fabbri, Fabio and Sami, Mariagiovanna}
}
@conference {60.FiSiSa07,
	title = {Security Aspects in Networks-on-Chips: Overview and Proposals for Secure Implementations},
	booktitle = {DSD07, in proceedings of 10th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD 07)},
	year = {2007},
	month = {August 29-31},
	address = {L{\"u}beck, Germany},
	abstract = {Security has gained increasing relevance in the development of embedded devices. Towards the aim of a secure system at each level of the design, in this paper we address security aspects related to Networks-on-Chips (NoCs) architectures. After presenting the attacks most likely to address NoCs, we survey existing academic and industrial secure architectures relevant to our case, focusing in particular on their communication infrastructure. We outline and propose possible solutions to contrast some of the attacks described and suggest the use of the NoC as a mean to monitor and detect unexpected system behaviors.},
	keywords = {embedded systems, multiprocessor system-on-chip (MPSoC), network-on-chip (NoC), security},
	doi = {http://dx.doi.org/10.1109/DSD.2007.4341520},
	author = {Fiorin, Leandro and Silvano, Cristina and Sami, Mariagiovanna}
}
@conference {56.FeTaSaMa07,
	title = {Self-adaptive Security at Application Level: a Proposal},
	booktitle = {ReCoSoC 2007, Jun. 2007, in proceedings of ReCoSoC 2007},
	year = {2007},
	month = {June},
	abstract = {Self-adaptive systems have the ability to adapt themselves to mutating external or internal conditions without requesting any intervention of the user; the security of such systems is influenced by those adaptations. Therefore, also the security mechanisms that are put in place by the operating system, should adapt to maintain the desired security level. This paper proposes a self-adaptive framework for the system security. This adaptation scheme allows the system to choose the best set of security policies at every given time; this set is determined by considering the system internal and external conditions as well as the application requirements. The proposed framework deals with self-adaptation at system level in order to provide both a domain independent and a flexible solution.},
	keywords = {autonomous systems, security, security policies, self-adaptive security, self-adaptive systems, system level design},
	author = {Ferrante, Alberto and Taddeo, Antonio Vincenzo and Sami, Mariagiovanna and Mantovani, Fabrizio and Fridkins, Jurijs}
}
@conference {50.MuPaNeSa07,
	title = {StateCharts to SystemC: a High Level Hardware Simulation Approach},
	booktitle = {Proceedings of GLSVLSI 2007},
	year = {2007},
	month = {March 11-13},
	address = {Stresa, Italy},
	abstract = {In this paper we present a tool that converts specifications written with a subset of StateCharts into SystemC behavioral models. The main advantages of such an approachare rapidity of use, simplicity and reusability. Various systems can be modeled at different levels of abstraction and accuracy through StateCharts and different peculiar aspects (e.g. energy, performances) can be taken into consideration. Moreover different parts of the design can be identified at different detail levels. The kernel of the simulator is fully discussed together with its mapping to the semantics of our StateCharts diagrams. As a case study we present here a model of the IBM PowerPC 750 Cache system and the respective SystemC simulator automatically generated by our tool.},
	keywords = {code generation, StateCharts, SystemC, unified modeling language (UML)},
	doi = {http://dx.doi.org/10.1145/1228784.1228904},
	author = {Mura, Marcello and Paolieri, Marco and Negri, Luca and Sami, Mariagiovanna}
}
@conference {31.1070384,
	title = {Flexible Power Modeling for Wireless Systems: Power Modeling and Optimization of two Bluetooth Implementations},
	booktitle = {WOWMOM {\textquoteright}05: Proceedings of the Sixth IEEE International Symposium on a World of Wireless Mobile and Multimedia Networks (WoWMoM{\textquoteright}05)},
	year = {2005},
	pages = {408{\textendash}416},
	publisher = {IEEE Computer Society},
	organization = {IEEE Computer Society},
	address = {Washington, DC, USA},
	abstract = {A large number of embedded multimedia applications are characterized by high instruction-level parallelism (ILP) expecially in the most critical internal loop bodies. Very Large Instruction Word (VLIW) architectures Application Specific Instruction Set Processors (ASIP) are best suited to exploit such parallelism. Fast design space exploration and optimization of VLIW architecture to a specific application target is increasingly becoming the crucial factor to achieve higher efficiency designs in a relatively small amount of time. In this paper we propose an example of VLIW architecture application driven optimization using the VEX (VLIW Example) system. A typical image processing application, the Imaging Pipeline, has been chosen as an example.},
	isbn = {0-7695-2342-0-01},
	doi = {http://dx.doi.org/10.1109/WOWMOM.2005.46},
	author = {Negri, Luca and Sami, Mariagiovanna and Tran, Que Dung and Zanetti, Davide}
}
@conference {29.SaMaRe2005,
	title = {Speeding Security on the Intel StrongARM},
	booktitle = {Embedded Intel Solutions},
	year = {2005},
	pages = {31-33},
	abstract = {With the increasing use of portable and wireless devices in the business and daily life, protecting sensitive information via encryption is becoming more and more crucial. ALaRI (Advanced Learning and Research Institute) has been conducting research aimed at improving the execution of security algorithms in embedded systems. Thanks to a donation from Intel, ALaRI has been able to develop several recommendations for implementing security efficiently on the Intel StrongARM architecture.},
	keywords = {embedded processors, instruction set extension, security},
	author = {Sami, Mariagiovanna and Macchetti, Marco and Regazzoni, Francesco}
}
@conference {16.1013323,
	title = {FSM{\textendash}based power modeling of wireless protocols: the case of bluetooth},
	booktitle = {ISLPED {\textquoteright}04: Proceedings of the 2004 international symposium on Low power electronics and design},
	year = {2004},
	pages = {369-374},
	publisher = {ACM Press, New York, USA},
	organization = {ACM Press, New York, USA},
	address = {Newport Beach, California, USA},
	abstract = {The proliferation of pervasive computing applications relying on battery-powered devices and wireless connectivity is posing great emphasis on the issue of power optimization. While node-level models and approaches have been widely discussed, a problem requiring even greater attention is that of power associated with the communication protocols. We propose a high-level modeling methodology based on Finite State Machines useful to predict the energy consumption of given communication tasks with very low computational cost, which can be applied to any protocol. We use this methodology to create a power model of Bluetooth that we characterize and validate experimentally on a real implementation.},
	keywords = {bluetooth, power modeling, wireless protocols},
	isbn = {1-58113-929-2},
	doi = {http://dx.doi.org/10.1109/LPE.2004.1349368},
	author = {Negri, Luca and Sami, Mariagiovanna and Macii, David and Terranegra, Alessandra}
}
@conference {9.SaSaSciSiZaZa2003,
	title = {A Methodology for efficient architectural exploration of energy-delay trade-offs for embedded systems},
	booktitle = {SAC 2003},
	year = {2003},
	month = {March},
	pages = {672-678},
	address = {Melbourne},
	abstract = {The main goal of this paper is to identify the best architecture of an embedded system by considering at the same time energy and delay, avoiding the comprehensive analysis of the architectural design space. We adopt the Energy-Delay Product (EDP) as the evaluation metric to compare the alternative architectures of the target system. The paper analyzes an extended adaptive random search algorithm (ADGREED) to efficiently explore the architectural design space. The ADGREED algorithm is a pseudo-random optimization algorithm that combines the best potentialities of the adaptive random search (ADRAS) and the Greedy deterministic algorithm. The analysis has been carried out through the architectural optimization of the memory subsystem of a real-word embedded system executing the set of Mediabench benchmarks for multimedia applications. The reported experimental results have shown a reduction up to one order of magnitude of the number of design alternatives analyzed during the exploration phase, while maintaining very high accuracy.},
	keywords = {design space exploration, embedded systems},
	doi = {http://dx.doi.org/10.1145/952532.952664},
	author = {Salvemini, Lorenzo and Sami, Mariagiovanna and Sciuto, Donatella and Silvano, Cristina and Zaccaria, Vittorio and Zafalon, Roberto}
}
@conference {6.BoSaSciSiZaZa2002,
	title = {Energy Estimation and Optimization of Embedded VLIW Processors based on Instruction Clustering},
	booktitle = {39th Design Automation Conference},
	year = {2002},
	month = {June 10-14},
	pages = {886-891},
	address = {New Orleans},
	abstract = {Aim of this paper is to propose a methodology for the definition of an instruction-level energy estimation framework for VLIW (Very Long Instruction Word) processors. The power modeling methodology is the key issue to define an effective energy-aware software optimisation strategy for state-of-the-art ILP (Instruction Level Parallelism) processors. The methodology is based on an energy model for VLIW processors that exploits instruction clustering to achieve an efficient and fine grained energy estimation. The approach aims at reducing the complexity of the characterization problem for VLIW processors from exponential, with respect to the number of parallel operations in the same very long instruction, to quadratic, with respect to the number of instruction clusters. Furthermore, the paper proposes a spatial scheduling algorithm based on a low-power reordering of the parallel operations within the same long instruction. Experimental results have been carried out on the Lx processor, a 4-issue VLIW core jointly designed by HPLabs and STMicroelectronics. The results have shown an average error of 1:9\% between the cluster-based estimation model and the reference design, with a standard deviation of 5:8\%. For the Lx architecture, the spatial instruction scheduling algorithm provides an average energy saving of 12\%.},
	keywords = {power estimation, VLIW architectures},
	doi = {http://dx.doi.org/10.1109/DAC.2002.1012747},
	author = {Bona, Andrea and Sami, Mariagiovanna and Sciuto, Donatella and Silvano, Cristina and Zaccaria, Vittorio and Zafalon, Roberto}
}
@conference {4.BonaSaSciSiZaZa2002,
	title = {An Instruction-Level Methodology for Power Estimation and Optimization of Embedded VLIW cores},
	booktitle = {DATE 2002},
	year = {2002},
	month = {March 4-8},
	pages = {1128},
	address = {Paris},
	abstract = {The overall goal of this work is to define an instruction-level power macro-modeling and characterization methodology for VLIW embedded processor cores. The approach presented in this paper is a major extension of the work previously proposed in [1-3], targeting an instruction-level energy model to evaluate the energy consumption associated with a program execution on a pipelined VLIW core. Our first goal is the reduction of the complexity of the processor{\textquoteright}s energy model, without reducing the accuracy of the results. The second goal is to show how the energy model can be further simplified by introducing a methodology to automatically cluster the whole Instruction Set with respect to their average energy cost, in order to con verge to an highly effective design of experiments for the actual characterization task. The paper describes also the application of the proposed model to a real industrial VLIW core (the Lx Architecture developed by HP Labs and STMicroelectronics), to validate the effectiveness and accuracy of the proposed methodology.},
	doi = {http://dx.doi.org/10.1109/DATE.2002.998484},
	author = {Bona, Andrea and Sami, Mariagiovanna and Sciuto, Donatella and Silvano, Cristina and Zaccaria, Vittorio and Zafalon, Roberto}
}
