@article {18570,
	title = {On Practical Discrete Gaussian Samplers For Lattice-Based Cryptography},
	journal = {IEEE Transaction on Computers},
	year = {In Press},
	author = {Howe, James and Khalid, Ayesha and Rafferty, Ciara and Regazzoni, Francesco and O{\textquoteright}Neill, Maire}
}
@conference {18573,
	title = {Compact, Scalable, and Efficient Gaussian Samplers for Lattice-Based Cryptography},
	booktitle = {Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS) 2018},
	year = {2018},
	author = {Khalid, Ayesha and Howe, James and Rafferty, Ciara and Regazzoni, Francesco and O{\textquoteright}Neil, Maire}
}
@conference {18559,
	title = {Exploring the Vulnerability of R-LWE Encryption to Fault Attacks},
	booktitle = {Workshop on Cryptography and Security in Computing Systems of the HiPEAC2018 Conference, CS2 {\textquoteright}18},
	year = {2018},
	publisher = {ACM},
	organization = {ACM},
	address = {New York, NY, USA},
	author = {Valencia, Felipe and Oder, Tobias and G{\"u}neysu, Tim and Regazzoni, Francesco}
}
@conference {18560,
	title = {The design space of the number theoretic transform: {A} survey},
	booktitle = {2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, {SAMOS} 2017, Pythagorion, Greece, July 17-20, 2017 (Invited)},
	year = {2017},
	doi = {10.1109/SAMOS.2017.8344640},
	url = {https://doi.org/10.1109/SAMOS.2017.8344640},
	author = {Valencia, Felipe and Khalid, Ayesha and O{\textquoteright}Sullivan, Elizabeth and Regazzoni, Francesco}
}
@article {18561,
	title = {An Investigation of Sources of Randomness Within Discrete Gaussian Sampling},
	journal = {IACR Cryptology ePrint Archive},
	volume = {2017},
	year = {2017},
	pages = {298},
	author = {Brannigan, S{\'e}amus and Smyth, Neil and Oder, Tobias and Valencia, Felipe and O{\textquoteright}Sullivan, Elizabeth and G{\"u}neysu, Tim and Regazzoni, Francesco}
}
@conference {18576,
	title = {Special Session Paper: Efficient Arithmetic for lattice-based Cryptography},
	booktitle = {Proceedings of the CODES+ISSS 2017},
	year = {2017},
	author = {O{\textquoteright}Sullivan, Elizabeth and Regazzoni, Francesco}
}
@article {18455,
	title = {A Framework for Disturbance Analysis in Smart Grids by Fault Injection},
	journal = {Springer Journal on "Computer Science - Research and Development"},
	year = {2016},
	month = {09/2016},
	abstract = {With growing complexity of electric power systems, a total number of disturbances is expected to increase. Analyzing these disturbances and understanding grid{\textquoteright}s behavior, when under a disturbance, is a pre-requisite for designing methods for boosting grid{\textquoteright}s stability. The main obstacle to the analysis is a lack of relevant data that are publicly available. In this paper, we design and implement a framework for emulation of grid disturbances by employing simula-tion and fault-injection techniques. We also present a case study on generating voltage sag related data. A foreseen usage of the framework considers mainly prototyping, root-cause analysis and design and comparison of methods for disturbance detection and prediction. },
	issn = {1865-2042},
	doi = {10.1007/s00450-016-0313-8},
	url = {http://dx.doi.org/10.1007/s00450-016-0313-8},
	author = {Kaitovi{\'c}, Igor and Obradovi{\'c}, Filip and Lukovi{\'c}, Slobodan and Malek, Miroslaw}
}
@conference {18562,
	title = {Lattice-based cryptography: From reconfigurable hardware to {ASIC}},
	booktitle = {2016 International Symposium on Integrated Circuits (ISIC)},
	year = {2016},
	month = {12/2016},
	publisher = {IEEE},
	organization = {IEEE},
	doi = {10.1109/isicir.2016.7829689},
	url = {https://doi.org/10.1109/isicir.2016.7829689},
	author = {Oder, Tobias and G{\"u}neysu, Tim and Valencia, Felipe and Khalid, Ayesha and O{\textquoteright}Neill, Maire and Regazzoni, Francesco}
}
@conference {18489,
	title = {Secure architectures of future emerging cryptography},
	booktitle = {International Conference on Computing Frontiers CF{\textquoteright}16},
	series = {Proceedings of the ACM International Conference on Computing Frontiers},
	year = {2016},
	month = {05/2016},
	pages = {315-322},
	publisher = {ACM New York},
	organization = {ACM New York},
	address = {Como, italy},
	abstract = {Funded under the European Union{\textquoteright}s Horizon 2020 research and innovation programme, SAFEcrypto will provide a new generation of practical, robust and physically secure post-quantum cryptographic solutions that ensure long-term security for future ICT systems, services and applications. The project will focus on the remarkably versatile field of Lattice-based cryptography as the source of computational hardness, and will deliver optimised public key security primitives for digital signatures and authentication, as well identity based encryption (IBE) and attribute based encryption (ABE). This will involve algorithmic and design optimisations, and implementations of lattice-based cryptographic schemes addressing cost, energy consumption, performance and physical robustness. As the National Institute of Standards and Technology (NIST) prepares for the transition to a post-quantum cryptographic suite B, urging organisations that build systems and infrastructures that require long-term security to consider this transition in architectural designs; the SAFEcrypto project will provide Proof-of-concept demonstrators of schemes for three practical real-world case studies with long-term security requirements, in the application areas of satellite communications, network security and cloud. The goal is to affirm Lattice-based cryptography as an effective replacement for traditional number-theoretic public-key cryptography, by demonstrating that it can address the needs of resource-constrained embedded applications, such as mobile and battery-operated devices, and of real-time high performance applications for cloud and network management infrastructures},
	keywords = {identity based encryption, lattice-based cryptography, physical attacks, public-key cryptography},
	isbn = {978-1-4503-4128-8},
	doi = {10.1145/2903150.2907756},
	url = {http://doi.acm.org/10.1145/2903150.2907756},
	author = {O{\textquoteright}Neill, Maire and O{\textquoteright}Sullivan, Elizabeth and McWilliams, Gavin and Saarinen, Markku-Juhani and Moore, Ciara and Khalid, Ayesha and Howe, James and Del Pino, Rafael and Abdalla, Michel and Regazzoni, Francesco and Valencia, Andres Felipe and G{\"u}neysu, Tim and Oder, Tobias and Waller, Adrian and Jones, Glyn and Barnett, Anthony and Griffin, Robert and Byrne, Andrew and Ammar, Bassem and Lund, David}
}
@conference {18487,
	title = {Standard lattices in hardware},
	booktitle = {Proceedings of the 53rd Annual Design Automation Conference DAC 2016},
	series = {Proceedings of DAC },
	year = {2016},
	month = {06/2016},
	pages = {162},
	publisher = {ACM},
	organization = {ACM},
	address = {Austin, TX, USA},
	abstract = {Lattice-based cryptography has gained credence recently as a replacement for current public-key cryptosystems, due to its quantum-resilience, versatility, and relatively low key sizes. To date, encryption based on the learning with errors (LWE) problem has only been investigated from an ideal lattice standpoint, due to its computation and size efficiencies. However, a thorough investigation of standard lattices in practice has yet to be considered. Standard lattices may be preferred to ideal lattices due to their stronger security assumptions and less restrictive parameter selection process.

In this paper, an area-optimised hardware architecture of a standard lattice-based cryptographic scheme is proposed. The design is implemented on a FPGA and it is found that both encryption and decryption fit comfortably on a Spartan-6 FPGA. This is the first hardware architecture for standard lattice-based cryptography reported in the literature to date, and thus is a benchmark for future implementations. Additionally, a revised discrete Gaussian sampler is proposed which is the fastest of its type to date, and also is the first to investigate the cost savings of implementing with λ/2-bits of precision.

Performance results are promising compared to the hardware designs of the equivalent ring-LWE scheme, which in addition to providing stronger security proofs; generate 1272 encryptions per second and 4395 decryptions per second.
},
	keywords = {encryption, hardware design, lattice-based cryptography, physical attack},
	isbn = {978-1-4503-4236-0},
	doi = {10.1145/2897937.2898037},
	url = {http://doi.acm.org/10.1145/2897937.2898037},
	author = {Howe, James and Moore, Ciara and O{\textquoteright}Neill, Maire and Regazzoni, Francesco and G{\"u}neysu, Tim and Beeden, K.}
}
@inbook {17996,
	title = {Self-Organizing Real-Time Services in Mobile Ad Hoc Networks},
	booktitle = {Self-Organization in Embedded Real-Time Systems},
	year = {2013},
	pages = {55-74},
	publisher = {Springer New York},
	organization = {Springer New York},
	isbn = {978-1-4614-1968-6},
	doi = {10.1007/978-1-4614-1969-3_3},
	url = {http://dx.doi.org/10.1007/978-1-4614-1969-3_3},
	author = {Kakuda, Yoshiaki and Ohta, Tomoyuki and Malek, Miroslaw},
	editor = {Higuera-Toledano, Teresa and Brinkschulte, Uwe and Rettberg, Achim}
}
@conference {18075,
	title = {Compact Implementation and Performance Evaluation of Block Ciphers in ATtiny Devices},
	booktitle = {Progress in Cryptology - Africacrypt},
	year = {2012},
	month = {July},
	address = {Ifrance, Morocco},
	author = {Eisenbarth, Thomas and Gong, Zheng and Gneysu, Tim and Heyse, Stefan and Indesteege, Sebastiaan and Kerckhof, St{\'e}phanie and Koeune, Francois and Nad, Tomislav and Plos, Thomas and Regazzoni, Francesco and Standaert, Fran{\c c}ois-Xavier and Oldenzeel, Loic Van Oldene}
}
@conference {18073,
	title = {Compact Implementation and Performance Evaluation of Hash Functions in ATtiny Devices},
	booktitle = {11th Smart Card Research and Advanced Application Conference (CARDIS)},
	year = {2012},
	month = {November},
	address = {Graz, Austria},
	author = {Balasch, Josep and Ege, Baris and Eisenbarth, Thomas and Grard, Benot and Gong, Zheng and Gneysu, Tim and Heyse, Stefan and Kerckhof, St{\'e}phanie and Koeune, Francois and Plos, Thomas and Poppelmann, Thomas and Regazzoni, Francesco and Standaert, Fran{\c c}ois-Xavier and Van Assche, Gilles and Van Keer, Ronny and Oldenzeel, Loic Van Oldene and von Maurich, Ingo}
}
@inbook {17695,
	title = {Dynamic Adaptation of Security and QoS in Energy-Harvesting Sensors Nodes},
	booktitle = {e-Business and Telecommunications},
	series = {Communications in Computer and Information Science},
	volume = {222},
	year = {2012},
	pages = {243-258},
	publisher = {Springer},
	organization = {Springer},
	address = { Berlin Heidelberg},
	keywords = {energy harvesting, priority, quality of service (QoS), security, wireless sensor networks},
	isbn = {978-3-642-25205-1},
	doi = {10.1007/978-3-642-25206-8_16},
	url = {http://dx.doi.org/10.1007/978-3-642-25206-8_16},
	author = {Taddeo, Antonio Vincenzo and Mura, Marcello and Ferrante, Alberto},
	editor = {Obaidat, Mohammad and Tsihrintzis, George and Filipe, Joaquim}
}
@inbook {17734,
	title = {The MULTICUBE Design Flow},
	booktitle = {Multi-objective Design Space Exploration of Multiprocessor SoC Architectures},
	year = {2011},
	pages = {3-17},
	publisher = {Springer New York},
	organization = {Springer New York},
	isbn = {978-1-4419-8836-2},
	doi = {10.1007/978-1-4419-8837-9_1},
	url = {http://dx.doi.org/10.1007/978-1-4419-8837-9_1},
	author = {Silvano, Cristina and Fornaciari, William and Palermo, Gianluca and Zaccaria, Vittorio and Castro, Fabrizio and Martinez, Marcos and Bocchio, Sara and Zafalon, Roberto and Avasare, Prabhat and Vanmeerbeeck, Geert and Ykman-Couvreur, Chantal and Wouters, Maryse and Kavka, Carlos and Onesti, Luka and Turco, Alessandro and Bondi, Umberto and Mariani, Giovanni and Posadas, Hector and Villar, Eugenio and Wu, Chris and Dongrui, Fan and Hao, Zhang},
	editor = {Silvano, Cristina and Fornaciari, William and Villar, Eugenio}
}
@inbook {139.Sietal2.2011,
	title = {MULTICUBE: Multi-Objective Design Space Exploration of Multi-Core Architectures},
	booktitle = {VLSI 2010 Annual Symposium},
	volume = {105},
	year = {2011},
	pages = {47-63},
	publisher = {Springer},
	organization = {Springer},
	address = {Netherlands},
	abstract = {Given the increasing complexity of Chip Multi-Processors (CMPs), a wide range of architecture parameters must be explored at design time to find the best trade-off in terms of multiple competing objectives (such as energy, delay, bandwidth, area, etc.) The design space of the target architectures is huge because it should consider all possible combinations of each hardware parameter (e.g., number of processors, processor issue width, L1 and L2 cache sizes, etc.). In this complex scenario, intuition and past experience of design architects is no more a sufficient condition to converge to an optimal design of the system. Indeed, Automatic Design Space Exploration (DSE) is needed to systematically support the analysis and quantitative comparison of a large amount of design alternatives in terms of multiple competing objectives (by means of Pareto analysis). The main goal of the MULTICUBE project consists of the definition of an automatic Design Space Exploration framework to support the design of next generation many-core architectures.},
	isbn = {978-94-007-1487-8},
	url = {http://dx.doi.org/10.1007/978-94-007-1488-5_4},
	author = {Silvano, Cristina and Fornaciari, William and Palermo, Gianluca and Zaccaria, Vittorio and Castro, Fabrizio and Martinez, Marcos and Bocchio, Sara and Zafalon, Roberto and Avasare, Prabhat and Vanmeerbeeck, Geert and Ykman-Couvreur, Chantal and Wouters, Maryse and Kavka, Carlos and Onesti, Luka and Turco, Alessandro and Bondi, Umberto and Mariani, Giovanni and Posadas, Hector and Villar, Eugenio and Wu, Chris and Dongrui, Fan and Hao, Zhang and Shibin, Tang}
}
@conference {129.Sietal.ISVLSI11,
	title = {Multicube: Multi-objective design space exploration of multi-core architectures},
	booktitle = {ISVLSI 2010: IEEE Annual Symposium on VLSI},
	year = {2010},
	month = {July},
	pages = {488{\textendash}493},
	address = {Lixouri, Kefalonia - Greece},
	abstract = {Technology trends enable the integration of many processor cores in a System-on-Chip (SoC). In these complex architectures, several architectural parameters can be tuned to find the best trade-off in terms of multiple metrics such as energy and delay. The main goal of the MULTICUBE project consists of the definition of an automatic Design Space Exploration framework to support the design of next generation many-core architectures.},
	doi = {http://dx.doi.org/10.1109/ISVLSI.2010.67},
	author = {Silvano, Cristina and Fornaciari, William and Palermo, Gianluca and Zaccaria, Vittorio and Castro, Fabrizio and Martinez, Marcos and Bocchio, Sara and Zafalon, Roberto and Avasare, Prabhat and Vanmeerbeeck, Geert and Ykman-Couvreur, Chantal and Wouters, Maryse and Kavka, Carlos and Onesti, Luka and Turco, Alessandro and Bondi, Umberto and Mariani, Giovanni and Posadas, Hector and Villar, Eugenio and Wu, Chris and Dongrui, Fan and Hao, Zhang and Shibin, Tang}
}
@inbook {17765,
	title = {IPSec Database Query Acceleration},
	booktitle = {E-business and Telecommunications},
	series = {Communications in Computer and Information Science},
	volume = {23},
	year = {2009},
	pages = {188-200},
	publisher = {Springer Berlin Heidelberg},
	organization = {Springer Berlin Heidelberg},
	isbn = {978-3-540-88652-5},
	doi = {10.1007/978-3-540-88653-2_14},
	url = {http://dx.doi.org/10.1007/978-3-540-88653-2_14},
	author = {Ferrante, Alberto and Chandra, Satish and Piuri, Vincenzo},
	editor = {Filipe, Joaquim and Obaidat, Mohammad}
}
@conference {97.Silvanoetal09,
	title = {MULTICUBE: Multi-Objective Design Space Exploration of Multiprocessor Architectures for Embedded Multimedia Applications},
	booktitle = {Proceedings of the DATE{\textquoteright}09 workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications},
	year = {2009},
	month = {April},
	address = {Nice, France},
	author = {Silvano, Cristina and Palermo, Gianluca and Zaccaria, Vittorio and Fornaciari, William and Zafalon, Roberto and Bocchio, Sara and Martinez, Marcos and Wouters, Maryse and Vanmeerbeeck, Geert and Avasare, Prabhat and Onesti, Luka and Kavka, Carlos and Bondi, Umberto and Mariani, Giovanni and Villar, Eugenio and Posadas, Hector and Wu, Chris and Dongrui, Fan and Hao, Zhang}
}
@conference {73.OtReLa07,
	title = {Rapid Creation of Application Models from Bandwidth Aware Core Graphs},
	booktitle = {Proceedings of: IP Based SoC Design 2007},
	year = {2007},
	month = {December 5-6},
	address = {Grenoble, France},
	abstract = {We present a methodology that allows rapid creation of application models from bandwidth aware core graphs that are available in the literature for a wide range of applications and we discuss their applicability to the rapid exploration of multiple Networks on Chip (NoCs) layout organizations. In a bandwidth aware core graph, each node represents a core and the numbers on the edges represent the bandwidth requirements between cores. We describe core graphs in a UML object model diagram and we then have an automatic code generation tool which produces a SystemC description whose behaviour results in a packet generation on every output connection that respects the bandwidth requirements specified in the core graph. We can then rapidly derive a NoC mapping in which a specific floorplan of the cores can be evaluated and compared with alternate floorplan options for rapid design space exploration.},
	keywords = {network-on-chip (NoC), rapid prototyping},
	author = {Otero, Jo{\~a}o and Regazzoni, Francesco and Lajolo, Marcello}
}
@conference {20.989053,
	title = {An ASIC design for a high speed implementation of the hash function SHA-256 (384, 512)},
	booktitle = {GLSVLSI {\textquoteright}04: Proceedings of the 14th ACM Great Lakes symposium on VLSI},
	year = {2004},
	pages = {421{\textendash}425},
	publisher = {ACM Press, New York, USA},
	organization = {ACM Press, New York, USA},
	address = {Boston, MA, USA},
	abstract = {An implementation of the hash functions SHA-256, 384 and 512 is presented, obtaining a high clock rate through a reduction of the critical path length, both in the Expander and in the Compressor of the hash scheme. The critical path is shown to be the smallest achievable. Synthesis results show that the new scheme can reach a clock rate well exceeding 1 GHz using a 0.13?m technology.},
	isbn = {1-58113-853-9},
	doi = {http://doi.acm.org/10.1145/988952.989053},
	author = {Dadda, Luigi and Macchetti, Marco and Owen, Jeff}
}
@conference {18.969266,
	title = {The Design of a High Speed ASIC Unit for the Hash Function SHA-256 (384,512)},
	booktitle = {DATE {\textquoteright}04: Proceedings of the conference on Design, automation and test in Europe},
	year = {2004},
	pages = {30070},
	publisher = {IEEE Computer Society},
	organization = {IEEE Computer Society},
	address = {Washington, DC, USA},
	abstract = {After recalling the basic algorithms published by NIST for implementing the hash functions SHA-256 (384, 512), a basic circuit characterized by a cascade of full adder arrays is given. Implementation options are discussed and two methods for improving speed are exposed: the delay balancing and the pipelining. An application of the former is first given, obtaining a circuit that reduces the length of the critical path by a full adder array. A pipelined version is then given, obtaining a reduction of two full adder arrays in the critical path. The two methods are afterwards combined and the results obtained through hardware synthesis are exposed, where a comparison between the new circuits is also given.},
	isbn = {0-7695-2085-5-3},
	doi = {http://dx.doi.org/10.1109/DATE.2004.1269207},
	author = {Dadda, Luigi and Macchetti, Marco and Owen, Jeff}
}
