@conference {18477,
	title = {Challenges in designing trustworthy cryptographic co-processors},
	booktitle = {IEEE International Symposium on Circuits and Systems (ISCAS) 2015},
	year = {2015},
	month = {09/2015},
	pages = {2009-2012},
	publisher = {IEEE},
	organization = {IEEE},
	address = {Lisbon, Portugal},
	abstract = {Security is becoming ubiquitous in our society. However, the vulnerability of electronic devices that implement the needed cryptographic primitives has become a major issue. This paper starts by presenting a comprehensive overview of the existing attacks to cryptography implementations. Thereafter, the state-of-the-art on some of the most critical aspects of designing cryptographic co-processors are presented. This analysis starts by considering the design of asymmetrical and symmetrical cryptographic primitives, followed by the discussion on the design and online testing of True Random Number Generation. To conclude, techniques for the detection of Hardware Trojans are also discussed},
	keywords = {asymmetrical cryptographic primitives, cryptography, hardware Trojan detection techniques},
	issn = {0271-4302 },
	doi = {10.1109/ISCAS.2015.7169070},
	url = {http://dx.doi.org/10.1109/ISCAS.2015.7169070},
	author = {Regazzoni, Francesco and Graves, Ricardo and Di Natale, Giorgio and Batina, Lejla and Bhasin, Shivam and Ege, Baris and Fournaris, Apostolos P. and Mentens, Nele and Picek, Stjepan and Rozic, Vladimir and Sklavos, Nicolas and Yang, Bohan}
}
@conference {18075,
	title = {Compact Implementation and Performance Evaluation of Block Ciphers in ATtiny Devices},
	booktitle = {Progress in Cryptology - Africacrypt},
	year = {2012},
	month = {July},
	address = {Ifrance, Morocco},
	author = {Eisenbarth, Thomas and Gong, Zheng and Gneysu, Tim and Heyse, Stefan and Indesteege, Sebastiaan and Kerckhof, St{\'e}phanie and Koeune, Francois and Nad, Tomislav and Plos, Thomas and Regazzoni, Francesco and Standaert, Fran{\c c}ois-Xavier and Oldenzeel, Loic Van Oldene}
}
@conference {18073,
	title = {Compact Implementation and Performance Evaluation of Hash Functions in ATtiny Devices},
	booktitle = {11th Smart Card Research and Advanced Application Conference (CARDIS)},
	year = {2012},
	month = {November},
	address = {Graz, Austria},
	author = {Balasch, Josep and Ege, Baris and Eisenbarth, Thomas and Grard, Benot and Gong, Zheng and Gneysu, Tim and Heyse, Stefan and Kerckhof, St{\'e}phanie and Koeune, Francois and Plos, Thomas and Poppelmann, Thomas and Regazzoni, Francesco and Standaert, Fran{\c c}ois-Xavier and Van Assche, Gilles and Van Keer, Ronny and Oldenzeel, Loic Van Oldene and von Maurich, Ingo}
}
@conference {159.LuVuKaEr12.MELECON,
	title = {Virtual Metering for Virtual PHEV Aggregation},
	booktitle = {Proceedings of the 16th IEEE Mediterranean Electrotechnical Conference (MELECON2012)},
	year = {2012},
	month = {March 25-28},
	address = {Yasmine Hammamet, Tunisia},
	abstract = {Technically sustainable solutions for integration of (PH)EVs in Smart Grid emerge as an important concern. We discuss the need for introduction of Virtual Aggregations supported by implementation of Virtual Meters in power system structures. We advocate our proposal with an evaluation of scenarios based on realistic data. The structure and functionalities of the Virtual Aggregator, as well as proposed enhancements on the Smart Grid side, are presented.},
	author = {Lukovi{\'c}, Slobodan and Vukmirovi{\'c}, Srdjan and Kaitovi{\'c}, Igor and Erdeljan, Aleksandar}
}
@inbook {141.aetherinbook.2011,
	title = {AETHER: Self-Adaptive Networked Entities: Autonomous Computing Elements for Future Pervasive Applications and Technologies},
	booktitle = {Reconfigurable Computing: From FPGAs to Hardware/Software Codesign},
	year = {2011},
	pages = {149{\textendash}184},
	publisher = {Springer},
	organization = {Springer},
	address = {New York, USA},
	abstract = {The AETHER project has laid the foundation of a complete new framework for designing and programming computing resources that live in changing environments and need to re-configure their objectives in a dynamic way. This chapter contributes to a strategic research agenda in the field of self-adaptive computing systems. It brings inputs to the reconfigurable hardware community and proposes directions to go for reconfigurable hardware and research on self-adaptive computing; it tries to identify some of the most promising future technologies for reconfiguration, while pointing out the main foreseen Challenges for reconfigurable hardware. This chapter presents the main solutions the AETHER project proposed for some of the major concerns in trying to engineer a self-adaptive computing system. The text exposes the AETHER vision of self-adaptation and its requirements. It describes and discusses the proposed solutions for tackling self-adaptivity at the various levels of abstractions. It exposes how the developed technologies could be put together in a real methodology and how self-adaptation could then be used in potential applications. Finally and based on lessons learned from AETHER, we discuss open issues and research opportunities and put those in perspective along other investigations and roadmaps.},
	isbn = {978-1-4614-0061-5},
	author = {Gamrat, Christian and Philippe, Jean-Marc and Jesshope, Chris and Shafarenko, Alex and Bisdounis, Labros and Bondi, Umberto and Ferrante, Alberto and Cabestany, Joan and Huebner, Michael and Parsinnen, Juha and Kadlec, Jiri and Danek, Martin and Tain, Benoit and Eisenbach, Susan and Auguin, Michel and Diguet, Jean-Philippe and Lenormand, Eric and Roux, Jean-Luc},
	editor = {Cardoso, Joao Manuel Pai and Huebner, Michael}
}
@conference {135.VuLuErKu10.2,
	title = {An enhanced workflow management for Utility Management System},
	booktitle = {Proceedings of the International Congress on Ultra Modern Telecommunications and Control Systems (ICUMT 2010)},
	year = {2010},
	month = {October 18-20},
	address = {Moscow, Russia},
	abstract = {The emerging computational grid infrastructure consists of widely distributed heterogeneous resources, which makes mapping of increasingly complex applications a very challenging task. Utility Management Systems (UMS) manage very large number of workflows with very high resource requirements and thereby optimization of resource utilization has to be adapted. In this work we propose architecture that implements a novel concept for dynamical execution of a scheduling algorithm using near real-time feedback from the execution monitoring process. An Artificial Neural Network (ANN) was trained for workflow scheduling. In the case study, we first perform experiments with same number of workflows and then introduce two additional in the system observing its behavior with and without proposed improvements. Performance tests show that significant improvements of overall execution time can be achieved by introducing adaptive Artificial Neural Network.},
	doi = {http://dx.doi.org/10.1109/ICUMT.2010.5676601},
	author = {Vukmirovi{\'c}, Srdjan and Lukovi{\'c}, Slobodan and Erdeljan, Aleksandar and Kuli{\'c}, Filip}
}
@conference {137.VuLuErKu10.3,
	title = {A Smart Metering Architecture as a step towards Smart Grid realization},
	booktitle = {Proceedings of the IEEE EnergyCon 2010},
	year = {2010},
	month = {December 18-22},
	address = {Bahrain},
	abstract = {Emerging concept of Smart Grids aims at increasing visibility and controllability of electricity grids boosting their operational efficiency, enabling novel enhanced services to customers and utilities at a same time. Successful realization of this concept will in great part depend on efficient management of tremendous amounts of data to be gathered and processed in very short time periods. In this work we propose a novel smart metering architecture to manage data collected from deployed smart meters logically encapsulated in form of virtual meters. The metering infrastructure is structured in the form of Advanced Metering Infrastructure (AMI). The architecture of Meter Data Management (MDM) system as well and its integration in Control Center structure of power system is described in details. The testing and verification of proposed solution is performed on data from power distribution company Vattenfall, Sweden.},
	doi = {http://dx.doi.org/10.1109/ENERGYCON.2010.5771705},
	author = {Vukmirovi{\'c}, Srdjan and Lukovi{\'c}, Slobodan and Erdeljan, Aleksandar and Kuli{\'c}, Filip}
}
@conference {122.VuErKuLu10,
	title = {Software architecture for Smart Metering systems with Virtual Power Plant},
	booktitle = {Proceedings of the 15th IEEE Mediterranean Electrotechnical Conference (MELECON2010)},
	year = {2010},
	month = {April},
	address = {La Valleta, Malta},
	abstract = {This paper presents a novel architecture for Smart Metering systems which enables their seamless, secure and efficient integration in wider SmartGrid software structures. Smart metering solutions represent one of the fastest evolving areas in the field of power distribution systems. There is an extensive interest of leading software vendors in the field, for development of architectures that can efficiently manage transmission, processing and storing of tremendous amount of data produced by such metering devices deployed at the end-end side. The integration of these systems into existing power system software architectures (outage management, workforce management, etc.) represents a major challenge for research community. In such an environment it is extremely important to adopt standardized data exchange mechanisms. The proposed architecture is conceived as modular and scalable structure so that it can help implementation of novel power distribution concepts such as Virtual Power Plants (VPPs). The proposed architecture has been successfully tested and verified in real-life operation as one of modules of Smart Metering system named Meter Data Management (MDM) developed by Telvent DMS Llc, Serbia.},
	doi = {http://dx.doi.org/10.1109/MELCON.2010.5476237},
	author = {Vukmirovi{\'c}, Srdjan and Erdeljan, Aleksandar and Kuli{\'c}, Filip and Lukovi{\'c}, Slobodan}
}
@conference {131.VuLuErKu10,
	title = {A solution for CIM based integraton of Meter Data Management in Control Center of a power system},
	booktitle = {Proceedings of the 2010 IEEE Workshop on Environmental, Energy, and Structural Monitoring Systems (EESMS{\textquoteright}10)},
	year = {2010},
	month = {September 9},
	address = {Taranto, Italy},
	abstract = {Modern power systems, in particular Control Center structures, involve more and more software applications in their normal operation. Such scenario urges for standardization of inter and intra processes communication and data exchange. In this work we propose a solution for seamless Meter Data Management (MDM) integration with Control Center structures through Common Information Model (CIM). The solution is implemented in form of a wrapper that adopts messages (i.e. payloads) to the standard requested form. The proposed solution has been verified using a simulation framework which emulates regular control and data.},
	keywords = {monitoring and control, system level modeling, virtual power plants},
	doi = {http://dx.doi.org/10.1109/EESMS.2010.5634169},
	author = {Vukmirovi{\'c}, Srdjan and Lukovi{\'c}, Slobodan and Erdeljan, Aleksandar and Kuli{\'c}, Filip}
}
@article {18064,
	title = {Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology},
	journal = {Springer Transactions on Computational Science},
	volume = {5430},
	year = {2009},
	month = {February},
	pages = {230{\textendash}243},
	author = {Regazzoni, Francesco and Eisenbarth, Thomas and Poschmann, Axel and Groschdl, Johann and Gurkaynak, Frank and Macchetti, Marco and Toprak, Zeynep and Pozzi, Laura and Paar, Christof and Leblebici, Yusuf and Ienne, Paolo}
}
@inbook {92.FiPaSi09.2,
	title = {Security in NoC},
	booktitle = {Networks-on-Chips: Theory and Practice},
	year = {2009},
	pages = {157-194},
	publisher = {Taylor and Francis Group, LLC - CRC Press},
	organization = {Taylor and Francis Group, LLC - CRC Press},
	abstract = {Future integrated systems will contain billion of transistors, composing tens to hundreds of IP cores. These IP cores, implementing emerging complex multimedia and network ap- plications, should be able to deliver rich multimedia and networking services. An efficient cooperation among these IP cores (e.g., efficient data transfers) can be achieved through utilization of the available resources. The design of such complex systems includes several challenges to be addressed. Among others one challenge is to design an on-chip interconnection network that should be able to efficiently connect the IP cores. Another challenge is to derive such an application mapping that will make efficient usage of the available hardware resources . An architecture that is able to accommodate such a high number of cores, satisfying the need for commu- nication and data transfers, is the Network-on-Chip (NoC) architecture. For these reasons Networks-on-Chip become a popular choice for designing the on-chip interconnect for Systems-on-Chip (MPSoCs), and are supported from the industry (such as the Ethereal NoC from Philips, the STNoC from STMicroelectronics and an 80-core NoC from Intel). As it is presented in , the key design challenges of emerging NoC design are a) the communication infrastructure, b) the communication paradigm selection and c) the application mapping optimization.},
	keywords = {network-on-chip (NoC), security},
	author = {Fiorin, Leandro and Palermo, Gianluca and Silvano, Cristina and Elmiligi, Haytham},
	editor = {Gebali, Fayez and El-Kharashi, Watheq}
}
@conference {89.ReEiBrIeKo,
	title = {Can knowledge regarding the presence of countermeasures against fault attacks simplify power attacks on cryptographic devices?},
	booktitle = {Proceedings of 23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS 08)},
	year = {2008},
	month = {October 1-3},
	abstract = {Side-channel attacks are nowadays a serious concern when implementing cryptographic algorithms. Powerful ways for gaining information about the secret key as well as various countermeasures against such attacks have been recently developed. Although it is well known that such attacks can exploit information leaked from different sources, most prior works have only addressed the problem of protecting a cryptographic device against a single type of attack. Consequently, there is very little knowledge on how a scheme for protecting a device against one type of side-channel attack may affect its vulnerability to other types of side-channel attacks. In this paper we focus on devices that include protection against fault injection attacks (using different error detection schemes) and explore whether the presence of such fault detection circuits affects the resistance against attacks based on power analysis. Using the AES S-Box as an example, we performed attacks on the unprotected implementation as well as modified implementations with parity check circuits or residue check circuits (mod3 and mod7). In particular, we focus on the question whether the knowledge of the presence of error detection circuitry in the cryptographic device can help an attacker who attempts to mount a power attack on the device. Our results show that the presence of error detection circuitry helps the attacker even if he is unaware of this circuitry, and that the benefit to the attacker increases with the number of check bits used for the purpose of error detection.},
	author = {Regazzoni, Francesco and Eisenbarth, Thomas and Breveglieri, Luca and Ienne, Paolo and Koren, Israel}
}
@conference {67.ReEiGr07,
	title = {Power Attacks Resistance of Cryptographic S-boxes with added Error Detection Circuits},
	booktitle = {proceedings of: {\textquoteright}22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT{\textquoteright}07)},
	year = {2007},
	month = {September 26-28},
	address = {Rome, Italy},
	abstract = {Many side-channel attacks on implementations of cryptographic algorithms have been developed in recent years demonstrating the ease of extracting the secret key. In response, various schemes to protect cryptographic devices against such attacks have been devised and some implemented in practice. Almost all of these protection schemes target an individual side-channel attack and consequently, it is not obvious whether a scheme for protecting the device against one type of side-channel attacks may make the device more vulnerable to another type of side-channel attacks. We examine in this paper the possibility of such a negative impact for the case where fault detection circuitry is added to a device (to protect it against fault injection attacks) and analyze the resistance of the modified device to power attacks. To simplify the analysis we focus on only one component in the cryptographic device (namely, the S-box in the AES and Kasumi ciphers), and perform power attacks on the original implementation and on a modified implementation with an added parity check circuit. Our results show that the presence of the parity check circuitry has a negative impact on the resistance of the device to power analysis attacks.},
	keywords = {cryptography, fault tolerance, reliable applications, side channel attacks},
	author = {Regazzoni, Francesco and Eisenbarth, Thomas and Gro{\ss}sch{\"a}dl, Johann and Breveglieri, Luca and Ienne, Paolo and Koren, Israel and Paar, Christof}
}
@conference {59.ReBaEi07,
	title = {Simulation-based Methodology for Evaluating DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies},
	booktitle = {International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS IC 07)},
	year = {2007},
	month = {July 16-19},
	address = {Samos, Greece},
	abstract = {This paper explores the resistance of MOS Current Mode Logic (MCML) against Differential Power Analysis (DPA) attacks. Circuits implemented in MCML, in fact, have unique characteristics both in terms of power consumption and the dependency of the power profile from the input signal pattern. Therefore, MCML is suitable to protect cryptographic hardware from DPA and similar side-channel attacks. In order to demonstrate the effectiveness of different logic styles against power analysis attacks, the non-linear bijective function of the Kasumi algorithm (known as substitution box S7) was implemented with CMOS and MCML technology, and a set of attacks was performed using power traces derived from SPICE-level simulations. Although all keys were discovered for CMOS, only very few attacks to MCML were successful.},
	keywords = {current mode logic (CML), differential power analysis (DPA), power simulation, side channel attacks},
	author = {Regazzoni, Francesco and Badel, St{\'e}phane and Eisenbarth, Thomas and Gro{\ss}sch{\"a}dl, Johann and Poschmann, Axel and Toprak, Zeynep and Macchetti, Marco and Pozzi, Laura and Paar, Christof and Leblebici, Yusuf and Ienne, Paolo}
}
